OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [init/] [vc/] [src/] [inpbuf.v] - Diff between revs 46 and 51

Show entire file | Details | Blame | View Log

Rev 46 Rev 51
Line 14... Line 14...
 History:
 History:
 01/04/2010  Initial version. <wsong83@gmail.com>
 01/04/2010  Initial version. <wsong83@gmail.com>
 12/05/2010  Use MPxP crossbars. <wsong83@gmail.com>
 12/05/2010  Use MPxP crossbars. <wsong83@gmail.com>
 17/04/2010  Remove unnecessary pipeline stages. <wsong83@gmail.com>
 17/04/2010  Remove unnecessary pipeline stages. <wsong83@gmail.com>
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
 
 09/06/2011  Remove the C-elements as muxes already have C-elements inside. <wsong83@gmail.com>
 
 
*/
*/
 
 
module inpbuf (/*AUTOARG*/
module inpbuf (/*AUTOARG*/
   // Outputs
   // Outputs
Line 113... Line 114...
         .divc  ( divcm    ),
         .divc  ( divcm    ),
         .doa   ( muxa     )
         .doa   ( muxa     )
         );
         );
 
 
   //c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
   //c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
   ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
   ctree #(.DW(2)) ACKT(.ci({ivma, rua}), .co(dia));
 
 
   assign di0m = rst_n ? di0 : 0;
   assign di0m = rst_n ? di0 : 0;
   assign di1m = rst_n ? di1 : 0;
   assign di1m = rst_n ? di1 : 0;
   assign di2m = rst_n ? di2 : 0;
   assign di2m = rst_n ? di2 : 0;
   assign di3m = rst_n ? di3 : 0;
   assign di3m = rst_n ? di3 : 0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.