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Line 21... |
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module outpbuf (/*AUTOARG*/
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module outpbuf (/*AUTOARG*/
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// Outputs
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// Outputs
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dia, do0, do1, do2, do3, dot, dovc, afc, vca,
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dia, do0, do1, do2, do3, dot, dovc, afc, vca,
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// Inputs
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// Inputs
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di0, di1, di2, di3, dit, doa, credit, vcr, rstn
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di0, di1, di2, di3, dit, doa, credit, vcr, rst_n
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);
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);
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parameter DW = 32; // data width
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parameter DW = 32; // data width
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parameter VCN = 4; // VC number
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parameter VCN = 4; // VC number
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parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
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parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
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parameter FCPD = 3; // the depth of the credit pipeline
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parameter FCPD = 3; // the depth of the credit pipeline
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Line 49... |
// vc requests in
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// vc requests in
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input [VCN-1:0] vcr;
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input [VCN-1:0] vcr;
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output [VCN-1:0] vca;
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output [VCN-1:0] vca;
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// active-low reset
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// active-low reset
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input rstn;
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input rst_n;
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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wire [VCN-1:0] vcro, vcg, vcgl, vcrm;
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wire [VCN-1:0] vcro, vcg, vcgl, vcrm;
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wire [SCN-1:0] doan, diad;
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wire [SCN-1:0] doan, diad;
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wire dian, diavc, diavcn, diat;
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wire dian, diavc, diavcn, diat;
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Line 65... |
FCU (
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FCU (
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.afc ( afc ),
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.afc ( afc ),
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.ro ( vcro ),
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.ro ( vcro ),
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.credit ( credit ),
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.credit ( credit ),
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.ri ( vcr ),
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.ri ( vcr ),
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.rst ( ~rstn )
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.rst ( ~rst_n )
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);
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);
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// VC arbiter
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// VC arbiter
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mutex_arb #(.wd(VCN)) Sch (.req(vcro), .gnt(vcg));
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mutex_arb #(.wd(VCN)) Sch (.req(vcro), .gnt(vcg));
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Line 77... |
generate
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generate
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for(i=0; i<VCN; i++)begin:SCEN
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for(i=0; i<VCN; i++)begin:SCEN
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c2 C (.a0(vcg[i]), .a1(diavcn), .q(vcgl[i]));
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c2 C (.a0(vcg[i]), .a1(diavcn), .q(vcgl[i]));
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end
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end
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endgenerate
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endgenerate
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assign diavcn = (~diavc)&rstn;
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assign diavcn = (~diavc)&rst_n;
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// output data buffer
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// output data buffer
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generate
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generate
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for(gsub=0; gsub<SCN; gsub++) begin:SC
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for(gsub=0; gsub<SCN; gsub++) begin:SC
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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.i1 ( di1[gsub] ),
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.i1 ( di1[gsub] ),
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.i2 ( di2[gsub] ),
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.i2 ( di2[gsub] ),
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.i3 ( di3[gsub] ),
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.i3 ( di3[gsub] ),
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.oa ( doan[gsub] )
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.oa ( doan[gsub] )
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);
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);
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assign doan[gsub] = (~doa)&rstn;
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assign doan[gsub] = (~doa)&rst_n;
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end // block: SC
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end // block: SC
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endgenerate
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endgenerate
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pipen #(.DW(FT))
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pipen #(.DW(FT))
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L0T (
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L0T (
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.d_in ( dit ),
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.d_in ( dit ),
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.d_in_a ( diat ),
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.d_in_a ( diat ),
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.d_out ( dot ),
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.d_out ( dot ),
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.d_out_a ( (~doa)&rstn )
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.d_out_a ( (~doa)&rst_n )
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);
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);
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ctree #(.DW(SCN+2)) ACKT (.ci({diavc,diat, diad}), .co(dia));
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ctree #(.DW(SCN+2)) ACKT (.ci({diavc,diat, diad}), .co(dia));
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pipen #(.DW(VCN))
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pipen #(.DW(VCN))
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LSV (
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LSV (
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.d_in ( vcgl ),
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.d_in ( vcgl ),
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.d_in_a ( diavc ),
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.d_in_a ( diavc ),
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.d_out ( dovc ),
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.d_out ( dovc ),
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.d_out_a ( (~doa)&rstn )
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.d_out_a ( (~doa)&rst_n )
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);
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);
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assign vca = dovc;
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assign vca = dovc;
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endmodule // outpbuf
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endmodule // outpbuf
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