OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [init/] [vc/] [src/] [rtu.v] - Diff between revs 42 and 45

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 42 Rev 45
Line 20... Line 20... 
 
 
 
 
module rtu (/*AUTOARG*/
 
module rtu (/*AUTOARG*/
 
   // Outputs
 
   // Outputs
 
   dia, dort,
 
   dia, dort,
 
   // Inputs
 
   // Inputs
 
   rstn, di0, di1, di2, di3, dit, divc, addrx, addry, doa
 
   rst_n, di0, di1, di2, di3, dit, divc, addrx, addry, doa
 
   );
 
   );
 
   parameter VCN = 2;
 
   parameter VCN = 2;
 
   parameter DIR = 0;
 
   parameter DIR = 0;
 
   parameter SN = 4;
 
   parameter SN = 4;
 
   parameter PD = 2;
 
   parameter PD = 2;
 
 
 
 
 
   input            rstn;
 
   input            rst_n;
 
   input [3:0]      di0, di1, di2, di3;
 
   input [3:0]      di0, di1, di2, di3;
 
   input [2:0]       dit;
 
   input [2:0]       dit;
 
   input [VCN-1:0]  divc;
 
   input [VCN-1:0]  divc;
 
   output           dia;
 
   output           dia;
 
 
 
 
Line 122... Line 122... 
   assign p1an = p2an;
 
   assign p1an = p2an;
 
 
 
 
 
   // p2 -> L -> p3
 
   // p2 -> L -> p3
 
 
 
 
 
   c2 CP2A  ( .a0(p2ad), .a1(p2avc), .q(p2a));
 
   c2 CP2A  ( .a0(p2ad), .a1(p2avc), .q(p2a));
 
   assign p2an = (~p2a) & rstn;
 
   assign p2an = (~p2a) & rst_n;
 
 
 
 
 
   pipen #(.DW(SN))
 
   pipen #(.DW(SN))
 
   L2R (
 
   L2R (
 
        .d_in    ( p2d     ),
 
        .d_in    ( p2d     ),
 
        .d_in_a  ( p2ad    ),
 
        .d_in_a  ( p2ad    ),
Line 150... Line 150... 
         .d_in    ( p3d   ),
 
         .d_in    ( p3d   ),
 
         .d_sel   ( p3vc  ),
 
         .d_sel   ( p3vc  ),
 
         .d_out_a ( pda[0])
 
         .d_out_a ( pda[0])
 
         );
 
         );
 
 
 
 
 
   assign p3an = (~p3a) & rstn;
 
   assign p3an = (~p3a) & rst_n;
 
 
 
 
 
   // pd pipeline
 
   // pd pipeline
 
   generate
 
   generate
 
      for(gbd=0; gbd<PD*2; gbd++) begin:RT
 
      for(gbd=0; gbd<PD*2; gbd++) begin:RT
 
         for(gvc=0; gvc<VCN; gvc++) begin:V
 
         for(gvc=0; gvc<VCN; gvc++) begin:V
Line 163... Line 163... 
               .d_in    ( pd[gbd][gvc]     ),
 
               .d_in    ( pd[gbd][gvc]     ),
 
               .d_in_a  ( pda[gbd][gvc]    ),
 
               .d_in_a  ( pda[gbd][gvc]    ),
 
               .d_out   ( pd[gbd+1][gvc]   ),
 
               .d_out   ( pd[gbd+1][gvc]   ),
 
               .d_out_a ( pdan[gbd+1][gvc] )
 
               .d_out_a ( pdan[gbd+1][gvc] )
 
               );
 
               );
 
            assign pdan[gbd+1][gvc] = (~pda[gbd+1][gvc])&rstn;
 
            assign pdan[gbd+1][gvc] = (~pda[gbd+1][gvc])&rst_n;
 
         end
 
         end
 
      end // block: RT
 
      end // block: RT
 
   endgenerate
 
   endgenerate
 
 
 
 
 
   // output
 
   // output

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.