| Line 26... |
Line 26... |
// Outputs
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// Outputs
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svcra, wvcra, nvcra, evcra, lvcra, sswa, wswa, nswa, eswa, lswa,
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svcra, wvcra, nvcra, evcra, lvcra, sswa, wswa, nswa, eswa, lswa,
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sosr, wosr, nosr, eosr, losr,
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sosr, wosr, nosr, eosr, losr,
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// Inputs
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// Inputs
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svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
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svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
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wosa, nosa, eosa, losa, rstn
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wosa, nosa, eosa, losa, rst_n
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);
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);
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parameter VCN = 4; // number of VCs
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parameter VCN = 4; // number of VCs
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input [VCN-1:0][3:0] svcr, nvcr, lvcr; // VC requests from input VCs
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input [VCN-1:0][3:0] svcr, nvcr, lvcr; // VC requests from input VCs
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| Line 42... |
Line 42... |
output [VCN-1:0][1:0] wswa, eswa;
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output [VCN-1:0][1:0] wswa, eswa;
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output [VCN-1:0] sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
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output [VCN-1:0] sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
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input [VCN-1:0] sosa, wosa, nosa, eosa, losa;
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input [VCN-1:0] sosa, wosa, nosa, eosa, losa;
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input rstn; // active-low reset
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input rst_n; // active-low reset
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wire [VCN-1:0][3:0] msvcr, mnvcr, mlvcr; // shuffled VC requests
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wire [VCN-1:0][3:0] msvcr, mnvcr, mlvcr; // shuffled VC requests
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wire [VCN-1:0][1:0] mwvcr, mevcr;
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wire [VCN-1:0][1:0] mwvcr, mevcr;
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wire [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; // configuration signals from VCA to Req CB
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wire [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; // configuration signals from VCA to Req CB
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| Line 96... |
Line 96... |
assign wvcra[i] = {wvcrai[i][0]|wvcrai[i][1]};
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assign wvcra[i] = {wvcrai[i][0]|wvcrai[i][1]};
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assign nvcra[i] = {nvcrai[i][0]|nvcrai[i][1]|nvcrai[i][2]|nvcrai[i][3]};
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assign nvcra[i] = {nvcrai[i][0]|nvcrai[i][1]|nvcrai[i][2]|nvcrai[i][3]};
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assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
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assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
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assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
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assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
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or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rstn);
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or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rst_n);
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or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rstn);
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or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rst_n);
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or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rstn);
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or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rst_n);
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or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rstn);
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or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rst_n);
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or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rstn);
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or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rst_n);
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or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rstn);
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or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rst_n);
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or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rstn);
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or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rst_n);
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or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rstn);
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or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rst_n);
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or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rstn);
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or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rst_n);
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or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rstn);
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or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rst_n);
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or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rstn);
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or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rst_n);
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or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rstn);
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or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rst_n);
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or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rstn);
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or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rst_n);
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or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rstn);
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or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rst_n);
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or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rstn);
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or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rst_n);
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or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rstn);
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or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rst_n);
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|
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and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
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and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
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and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
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and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
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and VCAOs2 (svcrai[i][2], (|svcrami[i][2]), svcraii[i][2]);
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and VCAOs2 (svcrai[i][2], (|svcrami[i][2]), svcraii[i][2]);
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and VCAOs3 (svcrai[i][3], (|svcrami[i][3]), svcraii[i][3]);
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and VCAOs3 (svcrai[i][3], (|svcrami[i][3]), svcraii[i][3]);
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| Line 307... |
Line 307... |
.c ( i2sr ),
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.c ( i2sr ),
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.cfg ( mscfg ),
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.cfg ( mscfg ),
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.ca ( ),
|
.ca ( ),
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.r ( svcrdy ),
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.r ( svcrdy ),
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.ra ( svcrdya ),
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.ra ( svcrdya ),
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.rst_n ( rstn )
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.rst_n ( rst_n )
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);
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);
|
|
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mrma #(.N(4*VCN), .M(VCN))
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mrma #(.N(4*VCN), .M(VCN))
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WVA (
|
WVA (
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.c ( i2wr ),
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.c ( i2wr ),
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.cfg ( mwcfg ),
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.cfg ( mwcfg ),
|
.ca ( ),
|
.ca ( ),
|
.r ( wvcrdy ),
|
.r ( wvcrdy ),
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.ra ( wvcrdya ),
|
.ra ( wvcrdya ),
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.rst_n ( rstn )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
mrma #(.N(2*VCN), .M(VCN))
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mrma #(.N(2*VCN), .M(VCN))
|
NVA (
|
NVA (
|
.c ( i2nr ),
|
.c ( i2nr ),
|
.cfg ( mncfg ),
|
.cfg ( mncfg ),
|
.ca ( ),
|
.ca ( ),
|
.r ( nvcrdy ),
|
.r ( nvcrdy ),
|
.ra ( nvcrdya ),
|
.ra ( nvcrdya ),
|
.rst_n ( rstn )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
mrma #(.N(4*VCN), .M(VCN))
|
mrma #(.N(4*VCN), .M(VCN))
|
EVA (
|
EVA (
|
.c ( i2er ),
|
.c ( i2er ),
|
.cfg ( mecfg ),
|
.cfg ( mecfg ),
|
.ca ( ),
|
.ca ( ),
|
.r ( evcrdy ),
|
.r ( evcrdy ),
|
.ra ( evcrdya ),
|
.ra ( evcrdya ),
|
.rst_n ( rstn )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
mrma #(.N(4*VCN), .M(VCN))
|
mrma #(.N(4*VCN), .M(VCN))
|
LVA (
|
LVA (
|
.c ( i2lr ),
|
.c ( i2lr ),
|
.cfg ( mlcfg ),
|
.cfg ( mlcfg ),
|
.ca ( ),
|
.ca ( ),
|
.r ( lvcrdy ),
|
.r ( lvcrdy ),
|
.ra ( lvcrdya ),
|
.ra ( lvcrdya ),
|
.rst_n ( rstn )
|
.rst_n ( rst_n )
|
);
|
);
|
|
|
generate
|
generate
|
for(i=0; i<VCN; i++) begin: OPC
|
for(i=0; i<VCN; i++) begin: OPC
|
delay DLY ( .q(vcrst_n[i+1]), .a(vcrst_n[i])); // dont touch
|
delay DLY ( .q(vcrst_n[i+1]), .a(vcrst_n[i])); // dont touch
|
