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[/] [async_sdm_noc/] [branches/] [init/] [vc/] [src/] [vca.v] - Diff between revs 42 and 45

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Line 26... Line 26...
   // Outputs
   // Outputs
   svcra, wvcra, nvcra, evcra, lvcra, sswa, wswa, nswa, eswa, lswa,
   svcra, wvcra, nvcra, evcra, lvcra, sswa, wswa, nswa, eswa, lswa,
   sosr, wosr, nosr, eosr, losr,
   sosr, wosr, nosr, eosr, losr,
   // Inputs
   // Inputs
   svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
   svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
   wosa, nosa, eosa, losa, rstn
   wosa, nosa, eosa, losa, rst_n
   );
   );
 
 
   parameter VCN = 4;           // number of VCs
   parameter VCN = 4;           // number of VCs
 
 
   input [VCN-1:0][3:0]            svcr, nvcr, lvcr; // VC requests from input VCs
   input [VCN-1:0][3:0]            svcr, nvcr, lvcr; // VC requests from input VCs
Line 42... Line 42...
   output [VCN-1:0][1:0]     wswa, eswa;
   output [VCN-1:0][1:0]     wswa, eswa;
 
 
   output [VCN-1:0]                 sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
   output [VCN-1:0]                 sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
   input [VCN-1:0]                  sosa, wosa, nosa, eosa, losa;
   input [VCN-1:0]                  sosa, wosa, nosa, eosa, losa;
 
 
   input                           rstn; // active-low reset
   input                           rst_n; // active-low reset
 
 
   wire [VCN-1:0][3:0]               msvcr, mnvcr, mlvcr; // shuffled VC requests
   wire [VCN-1:0][3:0]               msvcr, mnvcr, mlvcr; // shuffled VC requests
   wire [VCN-1:0][1:0]               mwvcr, mevcr;
   wire [VCN-1:0][1:0]               mwvcr, mevcr;
 
 
   wire [VCN-1:0][3:0][VCN-1:0]    wcfg, ecfg, lcfg; // configuration signals from VCA to Req CB
   wire [VCN-1:0][3:0][VCN-1:0]    wcfg, ecfg, lcfg; // configuration signals from VCA to Req CB
Line 96... Line 96...
         assign wvcra[i] = {wvcrai[i][0]|wvcrai[i][1]};
         assign wvcra[i] = {wvcrai[i][0]|wvcrai[i][1]};
         assign nvcra[i] = {nvcrai[i][0]|nvcrai[i][1]|nvcrai[i][2]|nvcrai[i][3]};
         assign nvcra[i] = {nvcrai[i][0]|nvcrai[i][1]|nvcrai[i][2]|nvcrai[i][3]};
         assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
         assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
         assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
         assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
 
 
         or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rstn);
         or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rst_n);
         or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rstn);
         or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rst_n);
         or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rstn);
         or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rst_n);
         or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rstn);
         or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rst_n);
         or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rstn);
         or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rst_n);
         or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rstn);
         or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rst_n);
         or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rstn);
         or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rst_n);
         or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rstn);
         or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rst_n);
         or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rstn);
         or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rst_n);
         or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rstn);
         or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rst_n);
         or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rstn);
         or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rst_n);
         or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rstn);
         or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rst_n);
         or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rstn);
         or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rst_n);
         or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rstn);
         or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rst_n);
         or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rstn);
         or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rst_n);
         or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rstn);
         or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rst_n);
 
 
         and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
         and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
         and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
         and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
         and VCAOs2 (svcrai[i][2], (|svcrami[i][2]), svcraii[i][2]);
         and VCAOs2 (svcrai[i][2], (|svcrami[i][2]), svcraii[i][2]);
         and VCAOs3 (svcrai[i][3], (|svcrami[i][3]), svcraii[i][3]);
         and VCAOs3 (svcrai[i][3], (|svcrami[i][3]), svcraii[i][3]);
Line 307... Line 307...
        .c     ( i2sr    ),
        .c     ( i2sr    ),
        .cfg   ( mscfg   ),
        .cfg   ( mscfg   ),
        .ca    (         ),
        .ca    (         ),
        .r     ( svcrdy  ),
        .r     ( svcrdy  ),
        .ra    ( svcrdya ),
        .ra    ( svcrdya ),
        .rst_n ( rstn    )
        .rst_n ( rst_n   )
        );
        );
 
 
   mrma #(.N(4*VCN), .M(VCN))
   mrma #(.N(4*VCN), .M(VCN))
   WVA (
   WVA (
        .c     ( i2wr    ),
        .c     ( i2wr    ),
        .cfg   ( mwcfg   ),
        .cfg   ( mwcfg   ),
        .ca    (         ),
        .ca    (         ),
        .r     ( wvcrdy  ),
        .r     ( wvcrdy  ),
        .ra    ( wvcrdya ),
        .ra    ( wvcrdya ),
        .rst_n ( rstn    )
        .rst_n ( rst_n   )
        );
        );
 
 
   mrma #(.N(2*VCN), .M(VCN))
   mrma #(.N(2*VCN), .M(VCN))
   NVA (
   NVA (
        .c     ( i2nr    ),
        .c     ( i2nr    ),
        .cfg   ( mncfg   ),
        .cfg   ( mncfg   ),
        .ca    (         ),
        .ca    (         ),
        .r     ( nvcrdy  ),
        .r     ( nvcrdy  ),
        .ra    ( nvcrdya ),
        .ra    ( nvcrdya ),
        .rst_n ( rstn    )
        .rst_n ( rst_n   )
        );
        );
 
 
   mrma #(.N(4*VCN), .M(VCN))
   mrma #(.N(4*VCN), .M(VCN))
   EVA (
   EVA (
        .c     ( i2er    ),
        .c     ( i2er    ),
        .cfg   ( mecfg   ),
        .cfg   ( mecfg   ),
        .ca    (         ),
        .ca    (         ),
        .r     ( evcrdy  ),
        .r     ( evcrdy  ),
        .ra    ( evcrdya ),
        .ra    ( evcrdya ),
        .rst_n ( rstn    )
        .rst_n ( rst_n   )
        );
        );
 
 
   mrma #(.N(4*VCN), .M(VCN))
   mrma #(.N(4*VCN), .M(VCN))
   LVA (
   LVA (
        .c     ( i2lr    ),
        .c     ( i2lr    ),
        .cfg   ( mlcfg   ),
        .cfg   ( mlcfg   ),
        .ca    (         ),
        .ca    (         ),
        .r     ( lvcrdy  ),
        .r     ( lvcrdy  ),
        .ra    ( lvcrdya ),
        .ra    ( lvcrdya ),
        .rst_n ( rstn    )
        .rst_n ( rst_n   )
        );
        );
 
 
   generate
   generate
      for(i=0; i<VCN; i++) begin: OPC
      for(i=0; i<VCN; i++) begin: OPC
         delay DLY ( .q(vcrst_n[i+1]), .a(vcrst_n[i])); // dont touch
         delay DLY ( .q(vcrst_n[i+1]), .a(vcrst_n[i])); // dont touch

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