URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [init/] [vc/] [syn/] [script/] [constraint.tcl] - Diff between revs 41 and 42

Rev 41	Rev 42
Line 23...	Line 23...
`set_ungroup ALLOC false`	`set_ungroup ALLOC false`


`######### break the timing loops in the design ##############`	`######### break the timing loops in the design ##############`

	`# the cross points in the VCA`
	`foreach_in_collection celln [get_references -hierarchical RCBB_*] {`
	`set_disable_timing [get_object_name $celln]/I1 -from B -to Z`
	`set_disable_timing [get_object_name $celln]/I0/U1 -from B -to Z`
	`set_disable_timing [get_object_name $celln]/I0/U3 -from A -to Z`
	`set_disable_timing [get_object_name $celln]/I3/U1 -from A -to Z`
	`set_disable_timing [get_object_name $celln]/I3/U2 -from A -to Z`

	`}`

	`set_disable_timing [get_cells ALLOC/VCAO] -from A -to Z`

`# set some timing path ending points`	`# set some timing path ending points`
`set DPD []`	`set DPD []`
`set DPA []`	`set DPA []`
`foreach_in_collection celln [get_references -hierarchical dc2_*] {`	`foreach_in_collection celln [get_references -hierarchical dc2_*] {`
`append_to_collection DPD [ get_pins [get_object_name $celln]/U1/B]`	`append_to_collection DPD [ get_pins [get_object_name $celln]/U1/B]`