OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [trunk/] [common/] [src/] [mrma.v] - Diff between revs 22 and 28

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 22 Rev 28
Line 17... Line 17...
   Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009.
   Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009.
 
 
 History:
 History:
 05/09/2009  Initial version. <wsong83@gmail.com>
 05/09/2009  Initial version. <wsong83@gmail.com>
 05/11/2009  Speed up the arbiter. <wsong83@gmail.com>
 05/11/2009  Speed up the arbiter. <wsong83@gmail.com>
 24/05/2011  Clean up for opensource. <wsong83@gmail.com>
 27/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
 
*/
*/
 
 
module mrma (/*AUTOARG*/
module mrma (/*AUTOARG*/
   // Outputs
   // Outputs
Line 43... Line 43...
   output [M-1:0][N-1:0] cfg;     // the generated configuration
   output [M-1:0][N-1:0] cfg;     // the generated configuration
   wire [N-1:0][M-1:0]     scfg;
   wire [N-1:0][M-1:0]     scfg;
 
 
   wire [M-1:0][N-1:0]     hs;    // match results
   wire [M-1:0][N-1:0]     hs;    // match results
   wire [M-1:0][N-1:0]   blk;     // blockage
   wire [M-1:0][N-1:0]   blk;     // blockage
   wire [N-1:0][M-1:0]   cblk;    // shuffled blockage
   wire [N-1:0][M-1:0]   sblk;    // shuffled blockage
   wire [M-1:0]   rblk;  // resource blockage
   wire [M-1:0]   rbi;   // resource blockage
   wire [N-1:0]   cblk;  // client blockage
   wire [N-1:0]   cbi;   // client blockage
   wire [N-1:0]   cg, cm; // client requests
   wire [N-1:0]   cg, cm; // client requests
   wire [M-1:0]   rg, rm; // resource requests
   wire [M-1:0]   rg, rm; // resource requests
 
 
   input                 rst_n; // active low reset
   input                 rst_n; // active low reset
 
 
Line 80... Line 80...
                      .rg   ( rg[i]       ),
                      .rg   ( rg[i]       ),
                      .cg   ( cg[j]       )
                      .cg   ( cg[j]       )
                      );
                      );
 
 
            // shuffle the blockage
            // shuffle the blockage
            assign cblk[j][i] = blk[i][j];
            assign sblk[j][i] = blk[i][j];
 
 
            // shuffle the configuration
            // shuffle the configuration
            assign scfg[j][i] = cfg[i][j];
            assign scfg[j][i] = cfg[i][j];
 
 
            // store the match results
            // store the match results
            c2p  C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j]));
            c2p  C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j]));
 
 
         end // block: Clm
         end // block: Clm
      end // block: Row
      end // block: Row
 
 
      // combine the row blockage and generate input requests
      // combine the row blockage and generate input requests
      for(i=0; i<M; i++) begin: RB
      for(i=0; i<M; i++) begin: RB
         assign rbi[i] = (|blk[i]) & rst_n;
         assign rbi[i] = (|blk[i]) & rst_n;
         and AND_RG (rm[i], r[i], ~ra[i], rst_n);
         and AND_RG (rm[i], r[i], ~ra[i], rst_n);
         ra[i] = |cfg[i];
         assign ra[i] = |cfg[i];
      end
      end
 
 
      // combine the column blockage and generate input requests
      // combine the column blockage and generate input requests
      for(j=0; j<N; j++) begin: CB
      for(j=0; j<N; j++) begin: CB
         assign cbi[j] = (|cblk[j]) & rst_n;
         assign cbi[j] = (|sblk[j]) & rst_n;
         and AND_CG (cm[j], c[j], ~ca[j], rst_n);
         and AND_CG (cm[j], c[j], ~ca[j], rst_n);
         assign ca[j] = |scfg[j];
         assign ca[j] = |scfg[j];
      end
      end
   endgenerate
   endgenerate
 
 
endmodule // im_arb
endmodule // mrma
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.