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Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009.
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Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009.
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History:
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History:
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05/09/2009 Initial version. <wsong83@gmail.com>
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05/09/2009 Initial version. <wsong83@gmail.com>
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05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
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05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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27/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module mrma (/*AUTOARG*/
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module mrma (/*AUTOARG*/
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// Outputs
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// Outputs
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output [M-1:0][N-1:0] cfg; // the generated configuration
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output [M-1:0][N-1:0] cfg; // the generated configuration
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wire [N-1:0][M-1:0] scfg;
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wire [N-1:0][M-1:0] scfg;
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wire [M-1:0][N-1:0] hs; // match results
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wire [M-1:0][N-1:0] hs; // match results
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wire [M-1:0][N-1:0] blk; // blockage
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wire [M-1:0][N-1:0] blk; // blockage
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wire [N-1:0][M-1:0] cblk; // shuffled blockage
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wire [N-1:0][M-1:0] sblk; // shuffled blockage
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wire [M-1:0] rblk; // resource blockage
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wire [M-1:0] rbi; // resource blockage
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wire [N-1:0] cblk; // client blockage
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wire [N-1:0] cbi; // client blockage
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wire [N-1:0] cg, cm; // client requests
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wire [N-1:0] cg, cm; // client requests
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wire [M-1:0] rg, rm; // resource requests
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wire [M-1:0] rg, rm; // resource requests
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input rst_n; // active low reset
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input rst_n; // active low reset
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.rg ( rg[i] ),
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.rg ( rg[i] ),
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.cg ( cg[j] )
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.cg ( cg[j] )
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);
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);
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// shuffle the blockage
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// shuffle the blockage
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assign cblk[j][i] = blk[i][j];
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assign sblk[j][i] = blk[i][j];
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// shuffle the configuration
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// shuffle the configuration
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assign scfg[j][i] = cfg[i][j];
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assign scfg[j][i] = cfg[i][j];
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// store the match results
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// store the match results
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c2p C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j]));
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c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j]));
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end // block: Clm
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end // block: Clm
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end // block: Row
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end // block: Row
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// combine the row blockage and generate input requests
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// combine the row blockage and generate input requests
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for(i=0; i<M; i++) begin: RB
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for(i=0; i<M; i++) begin: RB
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assign rbi[i] = (|blk[i]) & rst_n;
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assign rbi[i] = (|blk[i]) & rst_n;
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and AND_RG (rm[i], r[i], ~ra[i], rst_n);
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and AND_RG (rm[i], r[i], ~ra[i], rst_n);
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ra[i] = |cfg[i];
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assign ra[i] = |cfg[i];
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end
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end
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// combine the column blockage and generate input requests
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// combine the column blockage and generate input requests
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for(j=0; j<N; j++) begin: CB
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for(j=0; j<N; j++) begin: CB
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assign cbi[j] = (|cblk[j]) & rst_n;
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assign cbi[j] = (|sblk[j]) & rst_n;
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and AND_CG (cm[j], c[j], ~ca[j], rst_n);
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and AND_CG (cm[j], c[j], ~ca[j], rst_n);
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assign ca[j] = |scfg[j];
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assign ca[j] = |scfg[j];
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end
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end
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endgenerate
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endgenerate
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endmodule // im_arb
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endmodule // mrma
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