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[/] [async_sdm_noc/] [trunk/] [common/] [src/] [pipe4.v] - Diff between revs 22 and 28

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Rev 22 Rev 28
Line 13... Line 13...
 *** SystemVerilog is used ***
 *** SystemVerilog is used ***
 
 
 History:
 History:
 05/05/2009  Initial version. <wsong83@gmail.com>
 05/05/2009  Initial version. <wsong83@gmail.com>
 17/04/2011  Replace the common ack generation. <wsong83@gmail.com>
 17/04/2011  Replace the common ack generation. <wsong83@gmail.com>
 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
 26/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
 
*/
*/
 
 
// the router structure definitions
// the router structure definitions
`include "define.v"
`include "define.v"
Line 39... Line 39...
   output [SCN-1:0]  o0, o1, o2, o3;
   output [SCN-1:0]  o0, o1, o2, o3;
   input             oa;        // input ack
   input             oa;        // input ack
   output            ia;        // output ack
   output            ia;        // output ack
 
 
`ifdef ENABLE_EOF
`ifdef ENABLE_EOF
   input             o4;        // the eof bit
   output            o4;        // the eof bit
   output            i4;
   input             i4;
`endif
`endif
 
 
   // internal signals
   // internal signals
   wire [2*SCN-2:0]    tack;
   wire [SCN-1:0]    tack;
 
 
   // generate the ack line
   // generate the ack line
   genvar       i;
   genvar       i;
 
 
   // the data pipe stage
   // the data pipe stage
Line 59... Line 59...
      dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i]));
      dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i]));
   end endgenerate
   end endgenerate
 
 
   // the eof bit
   // the eof bit
`ifdef ENABLE_EOF
`ifdef ENABLE_EOF
   dc2 DD_DC4 (.d(i4),  .a(oa[SCN-1]),  .q(o4));
   dc2 DD_DC4 (.d(i4),  .a(oa),  .q(o4));
`endif
`endif
 
 
   // generate the input ack
   // generate the input ack
   assign tack = o0|o1|o2|o3;
   assign tack = o0|o1|o2|o3;
   ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia));
   ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia));

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