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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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History:
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History:
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10/12/2009 Initial version. <wsong83@gmail.com>
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10/12/2009 Initial version. <wsong83@gmail.com>
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23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com>
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23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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27/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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module rcb (/*AUTOARG*/
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module rcb (/*AUTOARG*/
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// Outputs
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// Outputs
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parameter DW = 1; // datawidth a port
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parameter DW = 1; // datawidth a port
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input [NN-1:0][DW-1:0] ireq; // input requests
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input [NN-1:0][DW-1:0] ireq; // input requests
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output [NN-1:0] ira; // ack for input requests
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output [NN-1:0] ira; // ack for input requests
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output [MN-1:0][DW-1:0] oreq; // output requests
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output [MN-1:0][DW-1:0] oreq; // output requests
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input [DW-1:0] ora; // ack for output requests
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input [MN-1:0] ora; // ack for output requests
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input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
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input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
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wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests
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wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests
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wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
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wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
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// generate variable
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// generate variable
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genvar i, j, k;
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genvar i, j, k;
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// request matrix
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// request matrix
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generate
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generate
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for (i=0; i<MN; i++) begin: EN
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for (i=0; i<MN; i++) begin: EN
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for (j=0; j<DW; j=j+1) begin: SC
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for (j=0; j<DW; j++) begin: SC
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for (k=0; k<NN; k=k+1) begin: IP
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for (k=0; k<NN; k++) begin: IP
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and AC (m[i][j][k], ireq[k][j], cfg[i][k]);
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and AC (m[i][j][k], ireq[k][j], cfg[i][k]);
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end
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end
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// the OR gates
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// the OR gates
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assign oreq[i][j] = |m[i][j];
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assign oreq[i][j] = |m[i][j];
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end
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end
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endgenerate
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endgenerate
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// ack matrix
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// ack matrix
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generate
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generate
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for (k=0; k<NN; k=k+1) begin: ENA
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for (k=0; k<NN; k++) begin: ENA
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for (i=0; i<MN; i=i+1) begin: OP
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for (i=0; i<MN; i++) begin: OP
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and AC (ma[k][i], ora[i], cfg[i][k]);
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and AC (ma[k][i], ora[i], cfg[i][k]);
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end
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end
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// the OR gates
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// the OR gates
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assign ira[k] = |ma[k];
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assign ira[k] = |ma[k];
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