OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [trunk/] [sdm/] [src/] [sdm_sch.v] - Diff between revs 22 and 28

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 22 Rev 28
Line 16... Line 16...
 For the detail structure, please refer to Section 6.3.1 of the thesis:
 For the detail structure, please refer to Section 6.3.1 of the thesis:
   Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
   Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
 
 
 History:
 History:
 28/09/2009  Initial version. <wsong83@gmail.com>
 28/09/2009  Initial version. <wsong83@gmail.com>
 25/05/2011  Clean up for opensource. <wsong83@gmail.com>
 27/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
 
*/
*/
 
 
// the router structure definitions
// the router structure definitions
`include "define.v"
`include "define.v"
 
 
module sdm_sch (/*AUTOARG*/
module sdm_sch (/*AUTOARG*/
   // Outputs
   // Outputs
   sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
   sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
   // Inputs
   // Inputs
   sreq, nreq, lreq, wreq, ereq
   sreq, nreq, lreq, wreq, ereq, rst_n
   );
   );
 
 
   parameter VCN = 2;           // the number of virtual circuits per port
   parameter VCN = 2;           // the number of virtual circuits per port
 
 
   // income requests
   // income requests
Line 227... Line 227...
         );
         );
 
 
   generate
   generate
      for(i=0; i<VCN; i++) begin: OPC
      for(i=0; i<VCN; i++) begin: OPC
         delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
         delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
         assign SOPrdy[i] = (~SOPblk[i])&SOPrst_n[i+1];
         assign SOPrdy[i] = (~SOPblk[i])&OPrst_n[i+1];
         assign WOPrdy[i] = (~WOPblk[i])&WOPrst_n[i+1];
         assign WOPrdy[i] = (~WOPblk[i])&OPrst_n[i+1];
         assign NOPrdy[i] = (~NOPblk[i])&NOPrst_n[i+1];
         assign NOPrdy[i] = (~NOPblk[i])&OPrst_n[i+1];
         assign EOPrdy[i] = (~EOPblk[i])&EOPrst_n[i+1];
         assign EOPrdy[i] = (~EOPblk[i])&OPrst_n[i+1];
         assign LOPrdy[i] = (~LOPblk[i])&LOPrst_n[i+1];
         assign LOPrdy[i] = (~LOPblk[i])&OPrst_n[i+1];
      end
      end
   endgenerate
   endgenerate
 
 
 
   assign OPrst_n[0] = rst_n;
 
 
`endif // !`ifndef ENABLE_MRMA
`endif // !`ifndef ENABLE_MRMA
 
 
endmodule // sdm_sch
endmodule // sdm_sch
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.