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#
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#
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# Synthesis script
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# Synthesis script
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# currently using the Nangate 45nm cell lib.
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# currently using the Nangate 45nm cell lib.
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#
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#
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# History:
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# History:
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# 26/05/2009 Initial version. <wsong83@gmail.com>
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# 31/05/2009 Initial version. <wsong83@gmail.com>
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set rm_top router
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set rm_top router
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set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1"
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set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1"
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# working directory
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# working directory
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# read in source codes
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# read in source codes
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source script/source.tcl
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source script/source.tcl
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# elaborate the design
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# elaborate the design
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elaborate ${rm_top} -parameters ${rm_para}
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elaborate ${rm_top} -parameters ${rm_para}
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rename_design ${current_design} router
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link
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link
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check_design
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check_design
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define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
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define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\"
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change_name -rules verilog -hierarchy
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change_name -rules verilog -hierarchy
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write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design
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write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design
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write_sdf -significant_digits 5 file/${current_design}.sdf
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write_sdf -significant_digits 5 file/${current_design}.sdf
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write_sdc file/${current_design}.sdc
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report_constraints -verbose
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report_constraints -verbose
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report_constraints
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report_constraints
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report_area
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report_area
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