URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] [ata/] [trunk/] [bench/] [verilog/] [ata_device.v] - Diff between revs 16 and 30

Rev 16	Rev 30
Line 36...	Line 36...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: ata_device.v,v 1.1 2001-08-16 10:01:05 rudi Exp $`	`// $Id: ata_device.v,v 1.2 2002-02-25 06:07:21 rherveille Exp $`
`//`	`//`
`// $Date: 2001-08-16 10:01:05 $`	`// $Date: 2002-02-25 06:07:21 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/08/16 10:01:05 rudi`
	`//`
	`// - Added Test Bench`
	`// - Added Synthesis scripts for Design Compiler`
	`// - Fixed minor bug in atahost_top`
	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

Line 103...	Line 109...
`begin`	`begin`
`dout = mem[ addr ];`	`dout = mem[ addr ];`
`dout_en = 1;`	`dout_en = 1;`
`end`	`end`

`always @(negedge ata_dior)`	`always @(posedge ata_dior)`
`begin`	`begin`
`dout_en = 0;`	`dout_en = 0;`
`end`	`end`

`always @(posedge ata_diow)`	`always @(posedge ata_diow)`
Line 387...	Line 393...


`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`

`No newline at end of file`	`No newline at end of file`