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[/] [ata/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 16 and 21

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Rev 16	Rev 21
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: test_bench_top.v,v 1.1 2001-08-16 10:01:05 rudi Exp $`	`// $Id: test_bench_top.v,v 1.2 2002-02-16 10:41:16 rherveille Exp $`
`//`	`//`
`// $Date: 2001-08-16 10:01:05 $`	`// $Date: 2002-02-16 10:41:16 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/08/16 10:01:05 rudi`
	`//`
	`// - Added Test Bench`
	`// - Added Synthesis scripts for Design Compiler`
	`// - Fixed minor bug in atahost_top`
	`//`
`//`	`//`
`//`	`//`
`//`	`//`
`//`	`//`

Line 200...	Line 206...
`assign ata_data = ata_doe ? ata_dout : 16'hzzzz;`	`assign ata_data = ata_doe ? ata_dout : 16'hzzzz;`

`// DUT: ATA Host`	`// DUT: ATA Host`
`atahost_top u0( //-- WISHBONE SYSCON signals`	`atahost_top u0( //-- WISHBONE SYSCON signals`
`.wb_clk_i( clk ),`	`.wb_clk_i( clk ),`
`.rst_nreset_i( rst ),`	`.arst_i( rst ),`
`.wb_rst_i( ~rst ),`	`.wb_rst_i( ~rst ),`

`//-- WISHBONE SLAVE signals`	`//-- WISHBONE SLAVE signals`
`.wb_cyc_i( wb_cyc_i ),`	`.wb_cyc_i( wb_cyc_i ),`
`.wb_stb_i( wb_stb_i ),`	`.wb_stb_i( wb_stb_i ),`
Line 216...	Line 222...
`.wb_sel_i( wb_sel_i ),`	`.wb_sel_i( wb_sel_i ),`
`.wb_we_i( wb_we_i ),`	`.wb_we_i( wb_we_i ),`
`.wb_inta_o( int ),`	`.wb_inta_o( int ),`

`//-- ATA signals`	`//-- ATA signals`
`.ata_resetn_pad_o( ata_rst_ ),`	`.resetn_pad_o( ata_rst_ ),`
`.ata_dd_pad_i( ata_din ),`	`.dd_pad_i( ata_din ),`
`.ata_dd_pad_o( ata_dout ),`	`.dd_pad_o( ata_dout ),`
`.ata_dd_pad_oe( ata_doe ),`	`.dd_padoe_o( ata_doe ),`
`.ata_da_pad_o( ata_da ),`	`.da_pad_o( ata_da ),`
`.ata_cs0n_pad_o( ata_cs0 ),`	`.cs0n_pad_o( ata_cs0 ),`
`.ata_cs1n_pad_o( ata_cs1 ),`	`.cs1n_pad_o( ata_cs1 ),`
`.ata_diorn_pad_o( ata_dior_ ),`	`.diorn_pad_o( ata_dior_ ),`
`.ata_diown_pad_o( ata_diow_ ),`	`.diown_pad_o( ata_diow_ ),`
`.ata_iordy_pad_i( ata_iordy ),`	`.iordy_pad_i( ata_iordy ),`
`.ata_intrq_pad_i( ata_intrq_r )`	`.intrq_pad_i( ata_intrq_r )`
`);`	`);`

`// ATA Device Model`	`// ATA Device Model`
`ata_device a0( .ata_rst_( ata_rst_ ),`	`ata_device a0( .ata_rst_( ata_rst_ ),`
`.ata_data( ata_data ),`	`.ata_data( ata_data ),`
Line 260...	Line 266...
`include "tests.v"	`include "tests.v"

`endmodule`	`endmodule`


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[/] [ata/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 16 and 21