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/////////////////////////////////////////////////////////////////////
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//// ////
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//// OCIDEC-1 ATA Controller ////
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//// Main Controller ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: atahost_controller.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
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//
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// $Date: 2002-02-16 10:42:17 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// file: controller.v
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// Change History:
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// description: OCIDEC1 OpenCores IDE controller type-1
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// author : Richard Herveille
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// rev.: 1.0 june 28th, 2001. Initial Verilog release
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// rev.: 1.0 june 28th, 2001. Initial Verilog release
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// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section.
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// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section.
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// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite.
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// rev.: 1.2 July 9th, 2001. Added "timescale". Undid "IORDY & INTRQ" rewrite.
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// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).
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// rev.: 1.3 July 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).
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// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
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// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
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//
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// OCIDEC1 supports:
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// $Log: not supported by cvs2svn $
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// -Common Compatible timing access to all connected devices
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module atahost_controller (clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen,
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module atahost_controller (clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen,
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always@(posedge clk)
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always@(posedge clk)
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PIOack <= PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)
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PIOack <= PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)
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endmodule
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endmodule
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