| Line 22... |
Line 22... |
// DA(2:0) 3bit binary coded adress
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// DA(2:0) 3bit binary coded adress
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// CS0- select command block registers
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// CS0- select command block registers
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// CS1- select control block registers
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// CS1- select control block registers
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`include "timescale.v"
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`include "timescale.v"
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`include "atahost_define.v"
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module atahost_top (wb_clk_i, rst_nreset_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o,
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wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o,
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ata_resetn_pad_o, ata_dd_pad_i, ata_dd_pad_o, ata_dd_pad_oe, ata_da_pad_o, ata_cs0n_pad_o,
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resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoen_o, da_pad_o, cs0n_pad_o,
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ata_cs1n_pad_o, ata_diorn_pad_o, ata_diown_pad_o, ata_iordy_pad_i, ata_intrq_pad_i);
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cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i);
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//
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//
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// Parameter declarations
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// Parameter declarations
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//
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//
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parameter TWIDTH = 8; // counter width
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parameter TWIDTH = 8; // counter width
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// PIO mode 0 settings (@100MHz clock)
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// PIO mode 0 settings (@100MHz clock)
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| Line 43... |
Line 44... |
// inputs & outputs
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// inputs & outputs
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//
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//
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// WISHBONE SYSCON signals
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// WISHBONE SYSCON signals
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input wb_clk_i; // master clock in
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input wb_clk_i; // master clock in
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input rst_nreset_i; // asynchronous active low reset
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input arst_i; // asynchronous reset
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input wb_rst_i; // synchronous active high reset
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input wb_rst_i; // synchronous reset
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// WISHBONE SLAVE signals
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// WISHBONE SLAVE signals
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input wb_cyc_i; // valid bus cycle input
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input wb_cyc_i; // valid bus cycle input
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input wb_stb_i; // strobe/core select input
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input wb_stb_i; // strobe/core select input
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output wb_ack_o; // strobe acknowledge output
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output wb_ack_o; // strobe acknowledge output
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| Line 62... |
Line 63... |
input [ 3:0] wb_sel_i; // Byte select signals
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input [ 3:0] wb_sel_i; // Byte select signals
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input wb_we_i; // Write enable input
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input wb_we_i; // Write enable input
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output wb_inta_o; // interrupt request signal
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output wb_inta_o; // interrupt request signal
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// ATA signals
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// ATA signals
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output ata_resetn_pad_o;
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output resetn_pad_o;
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input [15:0] ata_dd_pad_i;
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input [15:0] dd_pad_i;
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output [15:0] ata_dd_pad_o;
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output [15:0] dd_pad_o;
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output ata_dd_pad_oe;
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output dd_padoen_o;
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output [ 2:0] ata_da_pad_o;
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output [ 2:0] da_pad_o;
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output ata_cs0n_pad_o;
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output cs0n_pad_o;
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output ata_cs1n_pad_o;
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output cs1n_pad_o;
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output ata_diorn_pad_o;
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output diorn_pad_o;
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output ata_diown_pad_o;
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output diown_pad_o;
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input ata_iordy_pad_i;
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input iordy_pad_i;
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input ata_intrq_pad_i;
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input intrq_pad_i;
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//
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//
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// constant declarations
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// constant declarations
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//
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//
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parameter [3:0] DeviceId = 4'h1;
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parameter [3:0] DeviceId = 4'h1;
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| Line 107... |
Line 108... |
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/////////////////
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/////////////////
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// Module body //
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// Module body //
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/////////////////
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/////////////////
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// generate asynchronous reset level
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// arst_signal is either a wire or a NOT-gate
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wire arst_signal = arst_i ^ `ARST_LVL;
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// generate bus cycle / address decoder
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// generate bus cycle / address decoder
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wire w_acc = &wb_sel_i[1:0]; // word access
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wire w_acc = &wb_sel_i[1:0]; // word access
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wire dw_acc = &wb_sel_i; // double word access
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wire dw_acc = &wb_sel_i; // double word access
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// bus error
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// bus error
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| Line 123... |
Line 128... |
wire CONsel = wb_cyc_i & wb_stb_i & !(`ATA_ATA_ADR) & dw_acc;
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wire CONsel = wb_cyc_i & wb_stb_i & !(`ATA_ATA_ADR) & dw_acc;
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// generate registers
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// generate registers
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// generate register select signals
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// generate register select signals
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wire sel_ctrl = CONsel & wb_we_i & (wb_adr_i[5:2] == `ATA_CTRL_REG);
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wire sel_ctrl = CONsel & wb_we_i & (wb_adr_i == `ATA_CTRL_REG);
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wire sel_stat = CONsel & wb_we_i & (wb_adr_i[5:2] == `ATA_STAT_REG);
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wire sel_stat = CONsel & wb_we_i & (wb_adr_i == `ATA_STAT_REG);
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wire sel_PIO_cmdport = CONsel & wb_we_i & (wb_adr_i[5:2] == `ATA_PIO_CMD);
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wire sel_PIO_cmdport = CONsel & wb_we_i & (wb_adr_i == `ATA_PIO_CMD);
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// reserved 0x03-0x0f --
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// reserved 0x03-0x0f --
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// generate control register
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// generate control register
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always@(posedge wb_clk_i or negedge rst_nreset_i)
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always@(posedge wb_clk_i or negedge arst_signal)
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if (~rst_nreset_i)
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if (~arst_signal)
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begin
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begin
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CtrlReg[31:1] <= 0;
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CtrlReg[31:1] <= 0;
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CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line)
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CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line)
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end
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end
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else if (wb_rst_i)
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else if (wb_rst_i)
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| Line 152... |
Line 157... |
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// generate status register clearable bits
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// generate status register clearable bits
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reg dirq, int;
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reg dirq, int;
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always@(posedge wb_clk_i or negedge rst_nreset_i)
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always@(posedge wb_clk_i or negedge arst_signal)
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if (~rst_nreset_i)
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if (~arst_signal)
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begin
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begin
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int <= 1'b0;
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int <= 1'b0;
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dirq <= 1'b0;
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dirq <= 1'b0;
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end
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end
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else if (wb_rst_i)
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else if (wb_rst_i)
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| Line 179... |
Line 184... |
// to read the status register and access the PIO registers at the same time.
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// to read the status register and access the PIO registers at the same time.
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assign stat[0] = int;
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assign stat[0] = int;
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// generate PIO compatible / command-port timing register
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// generate PIO compatible / command-port timing register
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always@(posedge wb_clk_i or negedge rst_nreset_i)
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always@(posedge wb_clk_i or negedge arst_signal)
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if (~rst_nreset_i)
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if (~arst_signal)
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begin
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begin
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PIO_cmdport_T1 <= PIO_mode0_T1;
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PIO_cmdport_T1 <= PIO_mode0_T1;
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PIO_cmdport_T2 <= PIO_mode0_T2;
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PIO_cmdport_T2 <= PIO_mode0_T2;
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PIO_cmdport_T4 <= PIO_mode0_T4;
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PIO_cmdport_T4 <= PIO_mode0_T4;
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PIO_cmdport_Teoc <= PIO_mode0_Teoc;
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PIO_cmdport_Teoc <= PIO_mode0_Teoc;
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| Line 209... |
Line 214... |
// hookup controller section
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// hookup controller section
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//
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//
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atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
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atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
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u1 (
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u1 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.nReset(rst_nreset_i),
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.nReset(arst_signal),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.irq(irq),
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.irq(irq),
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.IDEctrl_rst(IDEctrl_rst),
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.IDEctrl_rst(IDEctrl_rst),
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.IDEctrl_IDEen(IDEctrl_IDEen),
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.IDEctrl_IDEen(IDEctrl_IDEen),
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.PIO_cmdport_T1(PIO_cmdport_T1),
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.PIO_cmdport_T1(PIO_cmdport_T1),
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| Line 225... |
Line 230... |
.PIOack(PIOack),
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.PIOack(PIOack),
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.PIOa(wb_adr_i[5:2]),
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.PIOa(wb_adr_i[5:2]),
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.PIOd(wb_dat_i[15:0]),
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.PIOd(wb_dat_i[15:0]),
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.PIOq(PIOq),
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.PIOq(PIOq),
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.PIOwe(wb_we_i),
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.PIOwe(wb_we_i),
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.RESETn(ata_resetn_pad_o),
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.RESETn(resetn_pad_o),
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.DDi(ata_dd_pad_i),
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.DDi(dd_pad_i),
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.DDo(ata_dd_pad_o),
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.DDo(dd_pad_o),
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.DDoe(ata_dd_pad_oe),
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.DDoe(dd_padoen_o),
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.DA(ata_da_pad_o),
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.DA(da_pad_o),
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.CS0n(ata_cs0n_pad_o),
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.CS0n(cs0n_pad_o),
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.CS1n(ata_cs1n_pad_o),
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.CS1n(cs1n_pad_o),
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.DIORn(ata_diorn_pad_o),
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.DIORn(diorn_pad_o),
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.DIOWn(ata_diown_pad_o),
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.DIOWn(diown_pad_o),
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.IORDY(ata_iordy_pad_i),
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.IORDY(iordy_pad_i),
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.INTRQ(ata_intrq_pad_i)
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.INTRQ(intrq_pad_i)
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);
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);
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//
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//
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// generate WISHBONE interconnect signals
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// generate WISHBONE interconnect signals
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//
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//
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| Line 266... |
Line 271... |
// assign DAT_O output
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// assign DAT_O output
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assign wb_dat_o = `ATA_ATA_ADR ? {16'h0000, PIOq} : Q;
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assign wb_dat_o = `ATA_ATA_ADR ? {16'h0000, PIOq} : Q;
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endmodule
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endmodule
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