| Line 6... |
Line 6... |
// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
|
// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
|
// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
|
// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
|
// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
|
// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
|
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
|
// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
|
// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
|
// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
|
|
// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter
|
|
|
// DeviceType: OCIDEC-1: OpenCores IDE Controller type1
|
// DeviceType: OCIDEC-1: OpenCores IDE Controller type1
|
// Features: PIO Compatible Timing
|
// Features: PIO Compatible Timing
|
// DeviceID: 0x01
|
// DeviceID: 0x01
|
// RevNo : 0x00
|
// RevNo : 0x00
|
| Line 22... |
Line 23... |
// DA(2:0) 3bit binary coded adress
|
// DA(2:0) 3bit binary coded adress
|
// CS0- select command block registers
|
// CS0- select command block registers
|
// CS1- select control block registers
|
// CS1- select control block registers
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "atahost_define.v"
|
|
|
|
module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
|
module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
|
wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o,
|
wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o,
|
resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o,
|
resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o,
|
cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i);
|
cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i);
|
//
|
//
|
// Parameter declarations
|
// Parameter declarations
|
//
|
//
|
|
parameter ARST_LVL = 1'b0; // asynchronous reset level
|
|
|
parameter TWIDTH = 8; // counter width
|
parameter TWIDTH = 8; // counter width
|
// PIO mode 0 settings (@100MHz clock)
|
// PIO mode 0 settings (@100MHz clock)
|
parameter PIO_mode0_T1 = 6; // 70ns
|
parameter PIO_mode0_T1 = 6; // 70ns
|
parameter PIO_mode0_T2 = 28; // 290ns
|
parameter PIO_mode0_T2 = 28; // 290ns
|
parameter PIO_mode0_T4 = 2; // 30ns
|
parameter PIO_mode0_T4 = 2; // 30ns
|
| Line 110... |
Line 112... |
// Module body //
|
// Module body //
|
/////////////////
|
/////////////////
|
|
|
// generate asynchronous reset level
|
// generate asynchronous reset level
|
// arst_signal is either a wire or a NOT-gate
|
// arst_signal is either a wire or a NOT-gate
|
wire arst_signal = arst_i ^ `ARST_LVL;
|
wire arst_signal = arst_i ^ ARST_LVL;
|
|
|
// generate bus cycle / address decoder
|
// generate bus cycle / address decoder
|
wire w_acc = &wb_sel_i[1:0]; // word access
|
wire w_acc = &wb_sel_i[1:0]; // word access
|
wire dw_acc = &wb_sel_i; // double word access
|
wire dw_acc = &wb_sel_i; // double word access
|
|
|
| Line 273... |
Line 275... |
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
