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/////////////////////////////////////////////////////////////////////
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//// ////
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//// OCIDEC-1 ATA/ATAPI-5 Controller ////
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//// Main Controller ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: atahost_top.v,v 1.6 2002-02-16 10:42:17 rherveille Exp $
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//
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// $Date: 2002-02-16 10:42:17 $
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// $Revision: 1.6 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// Project: AT Atachement interface
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// Change History:
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// ATA-3 rev7B compliant
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// Author: Richard Herveille
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// rev.: 1.0 June 29th, 2001. Initial Verilog release
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// rev.: 1.0 June 29th, 2001. Initial Verilog release
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// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
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// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
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// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
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// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
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// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
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// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
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// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
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// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.
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// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
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// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
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// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter
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// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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/////////////////////////////////////////////////////////////
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//
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// DeviceType: OCIDEC-1: OpenCores IDE Controller type1
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// DeviceType: OCIDEC-1: OpenCores IDE Controller type1
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// Features: PIO Compatible Timing
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// Features: PIO Compatible Timing
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// DeviceID: 0x01
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// DeviceID: 0x01
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// RevNo : 0x00
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// RevNo : 0x00
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//
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//
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//
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// Host signals:
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// Host signals:
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// Reset
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// Reset
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// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host.
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// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host.
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endmodule
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endmodule
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