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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Run-Once counter ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: ro_cnt.v,v 1.2 2002-02-16 10:42:17 rherveille Exp $
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//
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//
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// Counter.v, contains 1) run-once down-counter 2) general purpose up-down riple-carry counter
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// $Date: 2002-02-16 10:42:17 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// Author: Richard Herveille
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// Change History:
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// Rev. 1.0 June 27th, 2001. Initial Verilog release
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// $Log: not supported by cvs2svn $
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// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list.
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//
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//
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///////////////////////////
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///////////////////////////
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// run-once down-counter //
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// run-once down-counter //
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///////////////////////////
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///////////////////////////
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// counts D+1 cycles before generating 'DONE'
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// counts D+1 cycles before generating 'DONE'
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`include "timescale.v"
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`include "timescale.v"
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module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q, id);
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module ro_cnt (clk, nReset, rst, cnt_en, go, done, d, q);
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// parameter declaration
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// parameter declaration
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parameter SIZE = 8;
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parameter SIZE = 8;
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parameter UD = 1'b0; // default count down
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parameter ID = {SIZE{1'b0}}; // initial data after reset
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// inputs & outputs
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// inputs & outputs
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input clk; // master clock
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input clk; // master clock
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input nReset; // asynchronous active low reset
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input nReset; // asynchronous active low reset
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input rst; // synchronous active high reset
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input rst; // synchronous active high reset
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input cnt_en; // count enable
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input cnt_en; // count enable
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input go; // load counter and start sequence
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input go; // load counter and start sequence
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output done; // done counting
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output done; // done counting
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input [SIZE-1:0] d; // load counter value
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input [SIZE-1:0] d; // load counter value
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output [SIZE-1:0] q; // current counter value
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output [SIZE-1:0] q; // current counter value
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input [SIZE-1:0] id; // initial data after reset
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// variable declarations
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// variable declarations
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reg rci;
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reg rci;
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wire nld, rco;
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wire nld, rco;
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (~nReset)
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if (~nReset)
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rci <= #1 1'b0;
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rci <= #1 1'b0;
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else if (rst)
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else if (rst)
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rci <= #1 1'b0;
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rci <= #1 1'b0;
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else if (cnt_en)
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else //if (cnt_en)
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rci <= #1 (go | rci) & !rco;
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rci <= #1 go | (rci & !rco);
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assign nld = !go;
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assign nld = !go;
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// hookup counter
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// hookup counter
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ud_cnt #(SIZE) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en),
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ud_cnt #(SIZE, ID) cnt (.clk(clk), .nReset(nReset), .rst(rst), .cnt_en(cnt_en),
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.ud(1'b0), .nld(nld), .d(d), .q(q), .resd(id), .rci(rci), .rco(rco));
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.ud(UD), .nld(nld), .d(d), .q(q), .rci(rci), .rco(rco));
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// assign outputs
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// assign outputs
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assign done = rco;
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assign done = rco;
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endmodule
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endmodule
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