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[/] [ata/] [trunk/] [rtl/] [verilog/] [ocidec-2/] [atahost_controller.v] - Diff between revs 24 and 32

Rev 24	Rev 32
Line 34...	Line 34...
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`//`	`//`
`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: atahost_controller.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $`	`// $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $`
`//`	`//`
`// $Date: 2002-02-18 14:26:46 $`	`// $Date: 2002-05-19 06:05:28 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rherveille $`	`// $Author: rherveille $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
Line 212...	Line 212...
`always@(posedge clk)`	`always@(posedge clk)`
`if (PIOdone & (PIOa == 4'b0110) & PIOwe)`	`if (PIOdone & (PIOa == 4'b0110) & PIOwe)`
`SelDev <= #1 PIOd[4];`	`SelDev <= #1 PIOd[4];`

`// generate PIOgo signal`	`// generate PIOgo signal`
`reg dPIOreq, PIOgo;`	`always @(posedge clk or negedge nReset)`
`always@(posedge clk)`	`if (~nReset)`
	`begin`
	`dPIOreq <= #1 1'b0;`
	`PIOgo <= #1 1'b0;`
	`end`
	`else if (rst)`
	`begin`
	`dPIOreq <= #1 1'b0;`
	`PIOgo <= #1 1'b0;`
	`end`
	`else`
`begin`	`begin`
`dPIOreq <= #1 PIOreq & !PIOack;`	`dPIOreq <= #1 PIOreq & !PIOack;`
`PIOgo <= #1 PIOreq & !dPIOreq & IDEctrl_IDEen;`	`PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen;`
`end`	`end`

`//`	`//`
`// Hookup PIO access controller`	`// Hookup PIO access controller`
`//`	`//`