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/*----------------------------------------------------------------------------/
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/ This IP is an PIO interface. /
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/-----------------------------------------------------------------------------/
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/
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/ Copyright (C) 2018 Iulian Gheorghiu (morgoth.creator@gmail.com), all right reserved.
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/
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/ This IP file is an open source software. Redistribution and use of this IP in
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/ source and binary forms, with or without modification, are permitted provided
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/ that the following condition is met:
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/ 1. Redistributions of source code must retain the above copyright notice,
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/ this condition and the following disclaimer.
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/
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/ This software is provided by the copyright holder and contributors "AS IS"
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/ and any warranties related to this software are DISCLAIMED.
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/ The copyright owner or contributors be NOT LIABLE for any damages caused
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/ by use of this software.
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/----------------------------------------------------------------------------*/
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`timescale 1ns / 1ps
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`include "io_s_h.v"
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module pio_s #(
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parameter DINAMIC_IN_OUT_CONFIG = "FALSE",
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parameter IN_OUT_MASK_CONFIG = 8'h00,
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parameter USE_INTERRUPTS = "FALSE",
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parameter DINAMIC_INTERRUPT_CONFIG = "FALSE",
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parameter INTERRUPT_MASK_CONFIG = 8'h00,
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parameter INTERRUPT_UP_DN_EDGE_DETECT = 8'h00,
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parameter INTERRUPT_BOTH_EDGES_DETECT_MASK = 8'h00,
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parameter BUS_KEPPER_EN_MASK = 0,
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parameter BUS_PULL_UP_EN_MASK = 0,
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parameter BUS_PULL_DN_EN_MASK = 0,
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parameter ADDRESS = 0,
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parameter BUS_ADDR_DATA_LEN = 16
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)(
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input rst,
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input clk,
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input [BUS_ADDR_DATA_LEN-1:0]addr,
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input wr,
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input rd,
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input [7:0]bus_in,
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output reg[7:0]bus_out,
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output int,
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input int_rst,
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inout [7:0]io
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);
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reg [7:0]IO_DIR;
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reg [7:0]IO_OUT;
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reg [7:0]INTMASK;
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reg [7:0]INTFLAGS;
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reg [7:0]PINCTRL[0:7];
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reg [7:0]INT_DETECT_POSEDGE;
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reg [7:0]INT_DETECT_POSEDGE_n;
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reg [7:0]INT_DETECT_NEGEDGE;
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reg [7:0]INT_DETECT_NEGEDGE_n;
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wire cs_int = addr >= ADDRESS && addr < (ADDRESS + 32);
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wire rd_int = cs_int && rd;
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wire wr_int = cs_int && wr;
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integer cnt_detect;
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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begin
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IO_DIR <= 'h00;
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IO_OUT <= 'h00;
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INTMASK <= 'h00;
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INTFLAGS <= 'h00;
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INT_DETECT_POSEDGE_n <= 'h00;
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INT_DETECT_NEGEDGE_n <= 'h00;
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end
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else
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begin
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if(wr_int)
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begin
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case(addr[4:0])
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`PORT_DIR: IO_DIR <= bus_in;
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`PORT_DIRSET: IO_DIR <= IO_DIR | bus_in;
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`PORT_DIRCLR: IO_DIR <= IO_DIR & (~bus_in);
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`PORT_DIRTGL: IO_DIR <= IO_DIR ^ (~bus_in);
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`PORT_OUT: IO_OUT <= bus_in;
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`PORT_OUTSET: IO_OUT <= IO_OUT | bus_in;
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`PORT_OUTCLR: IO_OUT <= IO_OUT & (~bus_in);
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`PORT_OUTTGL: IO_OUT <= IO_OUT ^ (~bus_in);
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`PORT_INT0MASK: INTMASK <= bus_in;
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`PORT_INTFLAGS: INTFLAGS <= INTFLAGS & (~bus_in);
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`PORT_PIN0CTRL, `PORT_PIN1CTRL,
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`PORT_PIN2CTRL, `PORT_PIN3CTRL,
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`PORT_PIN4CTRL, `PORT_PIN5CTRL,
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`PORT_PIN6CTRL, `PORT_PIN7CTRL: PINCTRL[addr[2:0]] <= bus_in;
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endcase
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end
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else
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begin
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if(USE_INTERRUPTS == "TRUE")
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begin
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for (cnt_detect = 0; cnt_detect < 8; cnt_detect = cnt_detect + 1)
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begin
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if(INT_DETECT_POSEDGE_n[cnt_detect] != INT_DETECT_POSEDGE[cnt_detect])
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begin
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INTFLAGS[cnt_detect] <= 1'b1;
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INT_DETECT_POSEDGE_n[cnt_detect] <= ~INT_DETECT_POSEDGE_n[cnt_detect];
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end
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else if(INT_DETECT_NEGEDGE_n[cnt_detect] != INT_DETECT_NEGEDGE[cnt_detect])
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begin
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INTFLAGS[cnt_detect] <= 1'b1;
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INT_DETECT_NEGEDGE_n[cnt_detect] <= ~INT_DETECT_NEGEDGE_n[cnt_detect];
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end
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end
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end
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end
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end
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end
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always @ (*)
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begin
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bus_out <= 8'hz;
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if(rd_int)
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begin
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case(addr[4:0])
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`PORT_DIR,
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`PORT_DIRSET: bus_out <= DINAMIC_IN_OUT_CONFIG == "TRUE" ? IO_DIR : 'h00;
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`PORT_DIRCLR: bus_out <= DINAMIC_IN_OUT_CONFIG == "TRUE" ? ~IO_DIR : 'h00;
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`PORT_OUT,
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`PORT_OUTSET: bus_out <= IO_OUT;
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`PORT_OUTCLR: bus_out <= ~IO_OUT;
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`PORT_IN: bus_out <= io;
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`PORT_INT0MASK: bus_out <= USE_INTERRUPTS == "TRUE" ? (DINAMIC_INTERRUPT_CONFIG == "TRUE" ? INTMASK : INTERRUPT_MASK_CONFIG) : 0;
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`PORT_INTFLAGS: bus_out <= USE_INTERRUPTS == "TRUE" ? INTFLAGS : 0;
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`PORT_PIN0CTRL, `PORT_PIN1CTRL,
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`PORT_PIN2CTRL, `PORT_PIN3CTRL,
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`PORT_PIN4CTRL, `PORT_PIN5CTRL,
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`PORT_PIN6CTRL, `PORT_PIN7CTRL: bus_out <= USE_INTERRUPTS == "TRUE" ? PINCTRL[addr[2:0]] : 'h0;
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default: bus_out <= 'h00;
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endcase
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end
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end
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wire out_0 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[0] ? IO_OUT[0] : 1'bz) : (IN_OUT_MASK_CONFIG[0] ? IO_OUT[0] : 1'bz);
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wire out_1 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[1] ? IO_OUT[1] : 1'bz) : (IN_OUT_MASK_CONFIG[1] ? IO_OUT[1] : 1'bz);
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wire out_2 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[2] ? IO_OUT[2] : 1'bz) : (IN_OUT_MASK_CONFIG[2] ? IO_OUT[2] : 1'bz);
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wire out_3 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[3] ? IO_OUT[3] : 1'bz) : (IN_OUT_MASK_CONFIG[3] ? IO_OUT[3] : 1'bz);
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wire out_4 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[4] ? IO_OUT[4] : 1'bz) : (IN_OUT_MASK_CONFIG[4] ? IO_OUT[4] : 1'bz);
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wire out_5 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[5] ? IO_OUT[5] : 1'bz) : (IN_OUT_MASK_CONFIG[5] ? IO_OUT[5] : 1'bz);
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wire out_6 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[6] ? IO_OUT[6] : 1'bz) : (IN_OUT_MASK_CONFIG[6] ? IO_OUT[6] : 1'bz);
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wire out_7 = DINAMIC_IN_OUT_CONFIG == "TRUE" ? (IO_DIR[7] ? IO_OUT[7] : 1'bz) : (IN_OUT_MASK_CONFIG[7] ? IO_OUT[7] : 1'bz);
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assign io = {out_7, out_6, out_5, out_4, out_3, out_2, out_1, out_0};
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assign int = USE_INTERRUPTS == "TRUE" ?|INTFLAGS : 'h00;
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wire _int_mode_up_edge0 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[0] ? (PINCTRL[0][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[0][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[0] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[0] : INTERRUPT_UP_DN_EDGE_DETECT[0]);
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wire _int_mode_up_edge1 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[1] ? (PINCTRL[1][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[1][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[1] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[1] : INTERRUPT_UP_DN_EDGE_DETECT[1]);
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wire _int_mode_up_edge2 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[2] ? (PINCTRL[2][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[2][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[2] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[2] : INTERRUPT_UP_DN_EDGE_DETECT[2]);
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wire _int_mode_up_edge3 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[3] ? (PINCTRL[3][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[3][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[3] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[3] : INTERRUPT_UP_DN_EDGE_DETECT[3]);
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wire _int_mode_up_edge4 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[4] ? (PINCTRL[4][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[4][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[4] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[4] : INTERRUPT_UP_DN_EDGE_DETECT[4]);
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wire _int_mode_up_edge5 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[5] ? (PINCTRL[5][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[5][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[5] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[5] : INTERRUPT_UP_DN_EDGE_DETECT[5]);
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wire _int_mode_up_edge6 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[6] ? (PINCTRL[6][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[6][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[6] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[6] : INTERRUPT_UP_DN_EDGE_DETECT[6]);
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wire _int_mode_up_edge7 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[7] ? (PINCTRL[7][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[7][3:0] == `PORT_ISC_RISING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[7] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[7] : INTERRUPT_UP_DN_EDGE_DETECT[7]);
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wire [7:0]int_mode_up_edge = {_int_mode_up_edge7, _int_mode_up_edge6, _int_mode_up_edge5, _int_mode_up_edge4, _int_mode_up_edge3, _int_mode_up_edge2, _int_mode_up_edge1, _int_mode_up_edge0};
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wire _int_mode_dn_edge0 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[0] ? (PINCTRL[0][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[0][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[0] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[0] : ~INTERRUPT_UP_DN_EDGE_DETECT[0]);
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wire _int_mode_dn_edge1 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[1] ? (PINCTRL[1][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[1][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[1] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[1] : ~INTERRUPT_UP_DN_EDGE_DETECT[1]);
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wire _int_mode_dn_edge2 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[2] ? (PINCTRL[2][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[2][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[2] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[2] : ~INTERRUPT_UP_DN_EDGE_DETECT[2]);
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wire _int_mode_dn_edge3 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[3] ? (PINCTRL[3][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[3][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[3] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[3] : ~INTERRUPT_UP_DN_EDGE_DETECT[3]);
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wire _int_mode_dn_edge4 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[4] ? (PINCTRL[4][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[4][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[4] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[4] : ~INTERRUPT_UP_DN_EDGE_DETECT[4]);
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wire _int_mode_dn_edge5 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[5] ? (PINCTRL[5][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[5][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[5] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[5] : ~INTERRUPT_UP_DN_EDGE_DETECT[5]);
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wire _int_mode_dn_edge6 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[6] ? (PINCTRL[6][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[6][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[6] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[6] : ~INTERRUPT_UP_DN_EDGE_DETECT[6]);
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wire _int_mode_dn_edge7 = DINAMIC_INTERRUPT_CONFIG == "TRUE" ? (INTMASK[7] ? (PINCTRL[7][3:0] == `PORT_ISC_BOTHEDGES_gc) || (PINCTRL[7][3:0] == `PORT_ISC_FALLING_gc) : 1'b0) : (INTERRUPT_MASK_CONFIG[7] ? INTERRUPT_BOTH_EDGES_DETECT_MASK[7] : ~INTERRUPT_UP_DN_EDGE_DETECT[7]);
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wire [7:0]int_mode_dn_edge = {_int_mode_dn_edge7, _int_mode_dn_edge6, _int_mode_dn_edge5, _int_mode_dn_edge4, _int_mode_dn_edge3, _int_mode_dn_edge2, _int_mode_dn_edge1, _int_mode_dn_edge0};
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genvar cnt;
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generate
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for (cnt = 0; cnt < 8; cnt = cnt + 1)
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begin:POSEDGE
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always @ (posedge io[cnt] or posedge rst)
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begin
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if(USE_INTERRUPTS == "TRUE")
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begin
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if(rst)
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INT_DETECT_POSEDGE[cnt] <= 'h00;
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else if(INT_DETECT_POSEDGE_n[cnt] == INT_DETECT_POSEDGE[cnt] && int_mode_up_edge)
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INT_DETECT_POSEDGE[cnt] <= ~INT_DETECT_POSEDGE[cnt];
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end
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end
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end
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for (cnt = 0; cnt < 8; cnt = cnt + 1)
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begin:NEGEDGE
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always @ (negedge io[cnt] or posedge rst)
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begin
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if(USE_INTERRUPTS == "TRUE")
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begin
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if(rst)
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INT_DETECT_NEGEDGE[cnt] <= 'h00;
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else if(INT_DETECT_NEGEDGE_n[cnt] == INT_DETECT_NEGEDGE[cnt] && int_mode_dn_edge)
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INT_DETECT_NEGEDGE[cnt] <= ~INT_DETECT_NEGEDGE[cnt];
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end
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end
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end
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for (cnt = 0; cnt < 8; cnt = cnt + 1)
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begin:KEPPERS
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if (BUS_KEPPER_EN_MASK[cnt])
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begin
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KEEPER KEEPER_inst (
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.O(io[cnt]) // Keeper output (connect directly to top-level port)
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);
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end
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end
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for (cnt = 0; cnt < 8; cnt = cnt + 1)
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begin:PULLUPS
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if (BUS_PULL_UP_EN_MASK[cnt])
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begin
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PULLUP PULLUP_inst (
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.O(io[cnt]) // PullUp output (connect directly to top-level port)
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);
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end
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end
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for (cnt = 0; cnt < 8; cnt = cnt + 1)
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begin:PULLDOWNS
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if (BUS_PULL_DN_EN_MASK[cnt])
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begin
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PULLDOWN PULLDOWN_inst (
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.O(io[cnt]) // PullDown output (connect directly to top-level port)
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);
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end
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end
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endgenerate
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endmodule
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