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/*
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* This IP is a SPI IO adapter implementation.
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*
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* Copyright (C) 2018 Iulian Gheorghiu
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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`timescale 1ns / 1ps
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`include "io_s_h.v"
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module spi_s #(
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parameter DINAMIC_BAUDRATE = "TRUE",
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parameter BAUDRATE_DIVIDER = 3,
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parameter ADDRESS = 0,
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parameter BUS_ADDR_DATA_LEN = 16
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)(
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input rst,
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input clk,
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input [BUS_ADDR_DATA_LEN-1:0]addr,
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input wr,
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input rd,
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input [7:0]bus_in,
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output reg[7:0]bus_out,
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output int,
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output sck,/* SPI 'sck' signal (output) */
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output mosi,/* SPI 'mosi' signal (output) */
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input miso,/* SPI 'miso' signal (input) */
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output reg ss/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */
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);
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//reg [7:0]CTRL;
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//reg [7:0]BAUD;
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wire cs_int = addr >= ADDRESS && addr < (ADDRESS + 8);
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wire rd_int = cs_int && rd;
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wire wr_int = cs_int && wr;
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reg [7:0]baud_cnt;
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wire buffempty;
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reg [7:0]CTRL;
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reg [7:0]INTCTRL;
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reg [7:0]STATUS;
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localparam WORD_LEN = 8;
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localparam PRESCALLER_SIZE = 8;
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reg _mosi;
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reg charreceivedp;
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reg charreceivedn;
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reg inbufffullp = 1'b0;
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reg inbufffulln = 1'b0;
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reg [WORD_LEN - 1:0]input_buffer;
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reg [WORD_LEN - 1:0]output_buffer;
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assign buffempty = ~(inbufffullp ^ inbufffulln);
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reg [2:0]prescallerbuff;
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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begin
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inbufffullp <= 1'b0;
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prescallerbuff <= 3'b000;
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CTRL <= 0;
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INTCTRL <= 0;
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input_buffer <= 0;
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end
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else
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begin
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if(wr_int)
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begin
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case(addr[2:0])
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`SPI_CTRL: CTRL <= bus_in;
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`SPI_INTCTRL: INTCTRL <= bus_in;
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`SPI_DATA:
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begin
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if(inbufffullp == inbufffulln && buffempty && CTRL[`SPI_ENABLE_bp])
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begin
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inbufffullp <= ~inbufffullp;
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prescallerbuff <= {CTRL[`SPI_CLK2X_bp], CTRL[`SPI_PRESCALER_gp + 1:`SPI_PRESCALER_gp]};
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input_buffer <= bus_in;
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end
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end
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endcase
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end
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end
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end
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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begin
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STATUS <= 8'h00;
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charreceivedn <= 1'b0;
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end
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else if(rd_int)
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begin
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case(addr[2:0])
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`SPI_DATA: STATUS[`SPI_IF_bp] <= 1'b0;
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endcase
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end
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else if(charreceivedp != charreceivedn)
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begin
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STATUS[`SPI_IF_bp] <= 1'b1;
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charreceivedn <= ~charreceivedn;
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end
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end
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always @ (*)
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begin
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bus_out <= 8'bz;
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if(rd_int)
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begin
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case(addr[2:0])
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`SPI_CTRL: bus_out <= CTRL;
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`SPI_INTCTRL: bus_out <= INTCTRL;
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`SPI_STATUS: bus_out <= STATUS;
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`SPI_DATA: bus_out <= output_buffer;
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endcase
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end
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end
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assign int = INTCTRL[`SPI_INTLVL_gp + 1: `SPI_INTLVL_gp] ? STATUS[`SPI_IF_bp] : 1'b0;
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/***********************************************/
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/************ !Asynchronus send ****************/
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/***********************************************/
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localparam state_idle = 1'b0;
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localparam state_busy = 1'b1;
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reg state;
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reg [PRESCALLER_SIZE - 1:0]prescaller_cnt;
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reg [WORD_LEN - 1:0]shift_reg_out;
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reg [WORD_LEN - 1:0]shift_reg_in;
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reg [4:0]sckint;
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//reg sckintn;
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reg [2:0]prescallerint;
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reg [7:0]prescdemux;
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always @ (*)
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begin
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case(prescallerint)
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3'b000: prescdemux <= 3;
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3'b001: prescdemux <= 15;
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3'b010: prescdemux <= 63;
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3'b011: prescdemux <= 127;
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3'b100: prescdemux <= 1;
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3'b101: prescdemux <= 7;
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3'b110: prescdemux <= 31;
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3'b111: prescdemux <= 63;
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endcase
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end
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reg lsbfirstint;
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reg [1:0]modeint;
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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begin
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baud_cnt = 'h00;
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inbufffulln <= 1'b0;
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ss <= 1'b1;
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state <= state_idle;
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prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
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prescallerint <= {PRESCALLER_SIZE{3'b0}};
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shift_reg_out <= {WORD_LEN{1'b0}};
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shift_reg_in <= {WORD_LEN{1'b0}};
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sckint <= {5{1'b0}};
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_mosi <= 1'b1;
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output_buffer <= {WORD_LEN{1'b0}};
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charreceivedp <= 1'b0;
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lsbfirstint <= 1'b0;
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modeint <= 2'b00;
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end
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else
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begin
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if(CTRL[`SPI_ENABLE_bp])
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begin
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if(DINAMIC_BAUDRATE == "TRUE" ? baud_cnt == prescdemux : baud_cnt == {BAUDRATE_DIVIDER})
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begin
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baud_cnt <= 'h00;
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case(state)
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state_idle:
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begin
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if(inbufffullp != inbufffulln)
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begin
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inbufffulln <= ~inbufffulln;
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ss <= 1'b0;
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prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
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prescallerint <= prescallerbuff;
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lsbfirstint <= CTRL[`SPI_DORD_bp];
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modeint <= CTRL[`SPI_MODE_gp + 1:`SPI_MODE_gp];
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shift_reg_out <= input_buffer;
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state <= state_busy;
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if(!CTRL[`SPI_MODE_gp])
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begin
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if(!CTRL[`SPI_DORD_bp])
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_mosi <= input_buffer[WORD_LEN - 1];
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else
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_mosi <= input_buffer[0];
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end
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end
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end
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state_busy:
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begin
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if(prescaller_cnt != prescdemux)
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begin
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prescaller_cnt <= prescaller_cnt + 1;
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end
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else
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begin
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prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
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sckint <= sckint + 1;
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if(sckint[0] == modeint[0])
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begin
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if(!lsbfirstint)
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begin
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shift_reg_in <= {miso, shift_reg_in[7:1]};
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shift_reg_out <= {shift_reg_out[6:0], 1'b1};
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end
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else
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begin
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shift_reg_in <= {shift_reg_in[6:0], miso};
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shift_reg_out <= {1'b1, shift_reg_out[7:1]};
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end
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end
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else
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begin
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if(sckint[4:1] == WORD_LEN - 1)
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begin
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sckint <= {5{1'b0}};
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if(inbufffullp == inbufffulln)
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begin
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ss <= 1'b1;
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end
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output_buffer <= shift_reg_in;
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if(charreceivedp == charreceivedn)
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begin
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charreceivedp <= ~charreceivedp;
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end
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state <= state_idle;
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end
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else
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begin
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if(!lsbfirstint)
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_mosi <= shift_reg_out[WORD_LEN - 1];
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else
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_mosi <= shift_reg_out[0];
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end
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end
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end
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end
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endcase
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end
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else
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begin
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baud_cnt <= baud_cnt + 1;
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end
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end
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end
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end
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assign sck = (modeint[1])? ~sckint : sckint;
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assign mosi = (ss) ? 1'b1:_mosi;
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endmodule
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