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/*
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* This IP is a TWI IO adapter implementation.
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*
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* Copyright (C) 2018 Iulian Gheorghiu
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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`timescale 1ns / 1ps
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`include "io_s_h.v"
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module twi_s #(
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parameter DINAMIC_BAUDRATE = "TRUE",
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parameter BAUDRATE_DIVIDER = 255,
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parameter ADDRESS = 0,
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parameter BUS_ADDR_DATA_LEN = 16
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)(
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input rst,
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input clk,
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input [BUS_ADDR_DATA_LEN-1:0]addr,
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input wr,
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input rd,
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input [7:0]bus_in,
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output reg[7:0]bus_out,
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output int_tx_cmpl,
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output int_rx_cmpl,
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input int_tx_rst,
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input int_rx_rst,
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inout scl,
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inout sda
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);
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reg [7:0]CTRLA;
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reg [7:0]CTRLB;
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reg [7:0]CTRLC;
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reg [7:0]STATUS;
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reg [7:0]BAUD;
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reg [7:0]DATA;
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wire cs_int = addr >= ADDRESS && addr < (ADDRESS + 16);
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wire rd_int = cs_int && rd;
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wire wr_int = cs_int && wr;
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reg [7:0]baud_cnt;
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reg [1:0]cmd;
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reg tx_mode;
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reg start_sent;
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reg rcv_ack;
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reg send_ack;
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reg send_ack_st2;
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reg [1:0]stage;
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reg [2:0]bit_count;
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reg scl_int;
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reg sda_int;
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reg send_ack_int;
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localparam [2:0]CMD_NOP = {1'b1, 2'b00};
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localparam [2:0]CMD_RESTART = {1'b0, 2'b01};
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localparam [2:0]CMD_RECEIVE = {1'b0, 2'b10};
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localparam [2:0]CMD_STOP = {1'b0, 2'b11};
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always @ (*)
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begin
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bus_out <= 'hz;
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if(rd_int)
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begin
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case(addr[3:0])
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`TWI_MASTER_CTRLA: bus_out <= CTRLA;
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`TWI_MASTER_CTRLB: bus_out <= CTRLB;
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`TWI_MASTER_CTRLC: bus_out <= CTRLC;
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`TWI_MASTER_STATUS: bus_out <= STATUS;
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`TWI_MASTER_BAUD: bus_out <= BAUD;
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`TWI_MASTER_DATA: bus_out <= DATA;
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endcase
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end
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end
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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begin
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CTRLA <= 'h0;
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CTRLB <= 'h0;
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CTRLC <= 'h0;
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STATUS <= 'h0;
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BAUD <= 'h0;
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DATA <= 'h0;
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baud_cnt <= 'h00;
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cmd <= 'h00;
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tx_mode <= 1'b0;
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start_sent <= 1'b0;
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scl_int <= 1'b1;
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sda_int <= 1'b1;
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rcv_ack <= 1'b0;
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send_ack <= 1'b0;
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send_ack_st2 <= 1'b0;
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stage <= 'h00;
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send_ack_int <= 1'b1;
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end
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else
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begin
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if(DINAMIC_BAUDRATE == "TRUE" ? baud_cnt == BAUD : baud_cnt == {BAUDRATE_DIVIDER})
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begin
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baud_cnt <= 'h00;
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if(CTRLA[`TWI_MASTER_ENABLE_bp])
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begin
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case({tx_mode, cmd})
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CMD_NOP:
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begin
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if(~start_sent)
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begin/* Send the start sequence */
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stage <= stage + 1;
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case(stage)
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'h0:
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begin
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scl_int <= 1'b1;
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sda_int <= 1'b0;
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end
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'h1:
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begin
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scl_int <= 1'b0;
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bit_count <= 'hF;
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start_sent <= 1'b1;
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stage <= 'h0;
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end
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endcase
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end
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else
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begin/* Send bits */
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stage <= stage + 1;
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case(stage)
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'h0:
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begin
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case(rcv_ack)
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1'b0:
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begin
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sda_int <= DATA[bit_count];
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end
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1'b1:
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sda_int <= 1'b1;
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endcase
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end
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'h1:
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begin
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scl_int <= 1'b1;
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end
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'h2:
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begin
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if(rcv_ack)
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STATUS[`TWI_MASTER_RXACK_bp] <= sda;
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end
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'h3:
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begin
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stage <= 'h0;
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scl_int <= 1'b0;
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case(rcv_ack)
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1'b0:
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begin
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if(~|bit_count)
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rcv_ack <= 1'b1;
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bit_count <= bit_count - 1;
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end
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1'b1:
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begin
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tx_mode <= 1'b0;
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STATUS[`TWI_MASTER_WIF_bp] <= 1'b1;
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rcv_ack <= 1'b0;
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end
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endcase
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end
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endcase
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end
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end
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CMD_RESTART:
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begin/* Send restart */
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stage <= stage + 1;
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case(stage)
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'h0:
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begin
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sda_int <= 1'b1;
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end
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'h1:
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begin
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scl_int <= 1'b1;
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end
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'h2:
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begin
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sda_int <= 1'b0;
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end
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'h3:
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begin
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scl_int <= 1'b0;
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bit_count <= 'hF;
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start_sent <= 1'b1;
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stage <= 'h0;
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cmd <= 'h0;
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CTRLC[`TWI_MASTER_CMD_gp + 1:`TWI_MASTER_CMD_gp] <= 'h0;
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end
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endcase
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end
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CMD_RECEIVE:
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begin/* Receive bits */
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stage <= stage + 1;
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case(stage)
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'h0:
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begin
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if(send_ack && ~send_ack_st2)
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sda_int <= send_ack_int;
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else if(send_ack_st2)
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begin
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STATUS[`TWI_MASTER_RIF_bp] <= 1'b1;
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cmd <= 'h0;
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CTRLC[`TWI_MASTER_CMD_gp + 1:`TWI_MASTER_CMD_gp] <= 'h0;
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sda_int <= 1'b1;
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end
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end
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'h1:
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begin
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scl_int <= 1'b1;
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end
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'h2:
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begin
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if(~send_ack)
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DATA[bit_count] <= sda;
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end
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'h3:
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begin
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scl_int <= 1'b0;
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stage <= 'h0;
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case(send_ack)
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1'b0:
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begin
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if(~|bit_count)
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send_ack <= 1'b1;
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bit_count <= bit_count - 1;
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end
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1'b1: send_ack_st2 <= 1'b1;
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endcase
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end
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endcase
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end
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CMD_STOP:
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begin/* Send stop */
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stage <= stage + 1;
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case(stage)
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'h0: sda_int <= 1'b0;
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'h1: scl_int <= 1'b1;
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'h2:
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begin
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sda_int <= 1'b1;
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start_sent <= 1'b0;
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stage <= 'h0;
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cmd <= 'h0;
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CTRLC[`TWI_MASTER_CMD_gp + 1:`TWI_MASTER_CMD_gp] <= 'h0;
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end
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endcase
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end
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endcase
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end
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end
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else
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begin
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baud_cnt <= baud_cnt + 1;
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end
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if(CTRLA[`TWI_MASTER_ENABLE_bp])
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begin
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if(CTRLC[`TWI_MASTER_CMD_gp + 1:`TWI_MASTER_CMD_gp] && ~|cmd && ~tx_mode)
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begin
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cmd <= CTRLC[`TWI_MASTER_CMD_gp + 1:`TWI_MASTER_CMD_gp];
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stage <= 'h0;
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send_ack <= 1'b0;
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send_ack_st2 <= 1'b0;
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send_ack_int <= CTRLC[`TWI_SLAVE_ACKACT_bp];
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end
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end
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if(wr_int)
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begin
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case(addr[3:0])
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`TWI_MASTER_CTRLA: CTRLA <= bus_in;
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`TWI_MASTER_CTRLB: CTRLB <= bus_in;
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`TWI_MASTER_CTRLC: CTRLC <= bus_in;
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`TWI_MASTER_STATUS: STATUS <= STATUS ^ bus_in;
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`TWI_MASTER_BAUD: BAUD <= bus_in;
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//`TWI_MASTER_ADDR: ADDR <= bus_in;
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`TWI_MASTER_DATA:
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begin
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if(~|CTRLC[`TWI_MASTER_CMD_gp + 1:`TWI_MASTER_CMD_gp])
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begin
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DATA <= bus_in;
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tx_mode <= 1'b1;
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STATUS[`TWI_MASTER_WIF_bp] <= 1'b0;
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end
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end
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endcase
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end
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if(rd_int)
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begin
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case(addr[3:0])
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`TWI_MASTER_DATA:
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begin
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STATUS[`TWI_MASTER_RIF_bp] <= 1'b0;
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end
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endcase
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end
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end
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end
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PULLUP PULLUP_scl_inst (
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.O(scl) // 1-bit output: Pullup output (connect directly to top-level port)
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);
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PULLUP PULLUP_sda_inst (
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.O(sda) // 1-bit output: Pullup output (connect directly to top-level port)
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);
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assign scl = scl_int ? 1'bz : scl_int;
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assign sda = sda_int ? 1'bz : sda_int;
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endmodule
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