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/*
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* This is the simulation file for TWI IP.
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*
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* Copyright (C) 2018 Iulian Gheorghiu
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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`timescale 1ns / 1ps
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`include "io_s_h.v"
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module sim_i2c(
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output reg rst,
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output reg clk,
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output reg [15:0]addr,
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output reg wr,
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output reg rd,
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output [7:0]bus_in,
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output reg [7:0]bus_out,
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output int_tx_cmpl,
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output int_rx_cmpl,
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output int_tx_rst,
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output int_rx_rst,
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inout scl,
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inout sda
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);
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always #(1) clk <= ~clk; // clocking device
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initial
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begin
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rst = 0;
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clk = 1;
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wr = 0;
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rd = 0;
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#2;
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rst = 1;
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#2;
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rst = 0;
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#4;
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addr = `TWI_MASTER_BAUD;
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bus_out = 'h1;
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wr = 1;
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#2;
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addr = `TWI_MASTER_CTRLA;
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bus_out = `TWI_MASTER_ENABLE_bm;
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#2;
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addr = `TWI_MASTER_DATA;
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bus_out = 8'h55;
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#2;
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wr = 0;
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bus_out = 'hz;
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rd = 1;
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addr = `TWI_MASTER_STATUS;
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#2;
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while(~bus_in[`TWI_MASTER_WIF_bp]) #2;
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rd = 0;
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#2;
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wr = 1;
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addr = `TWI_MASTER_DATA;
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bus_out = 8'hAA;
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#2;
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wr = 0;
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bus_out = 'hz;
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rd = 1;
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addr = `TWI_MASTER_STATUS;
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#2;
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while(~bus_in[`TWI_MASTER_WIF_bp]) #2;
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rd = 0;
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#2;
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addr = `TWI_MASTER_CTRLC;
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bus_out = `TWI_MASTER_CMD_REPSTART_gc;
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#2;
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wr = 1;
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addr = `TWI_MASTER_CTRLC;
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bus_out = `TWI_MASTER_CMD_RECVTRANS_gc;
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#2;
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wr = 0;
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bus_out = 'hz;
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rd = 1;
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addr = `TWI_MASTER_STATUS;
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#2;
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while(~bus_in[`TWI_MASTER_RIF_bp]) #2;
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addr = `TWI_MASTER_DATA;
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#2;
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rd = 0;
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#2;
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wr = 1;
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addr = `TWI_MASTER_CTRLC;
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bus_out = `TWI_MASTER_ACKACT_bm | `TWI_MASTER_CMD_RECVTRANS_gc;
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#2;
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wr = 0;
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bus_out = 'hz;
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rd = 1;
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addr = `TWI_MASTER_STATUS;
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#2;
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while(~bus_in[`TWI_MASTER_RIF_bp]) #2;
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addr = `TWI_MASTER_DATA;
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#2;
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rd = 0;
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#2;
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wr = 1;
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addr = `TWI_MASTER_CTRLC;
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bus_out = `TWI_MASTER_CMD_STOP_gc;
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#2;
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wr = 0;
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bus_out = 'hz;
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#10;
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$finish;
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end
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twi_s #(
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.DINAMIC_BAUDRATE("TRUE"),
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.BAUDRATE_DIVIDER(19200),
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.ADDRESS(0),
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.BUS_ADDR_DATA_LEN(16)
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)twi_inst(
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.rst(rst),
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.clk(clk),
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.addr(addr),
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.wr(wr),
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.rd(rd),
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.bus_in(bus_out),
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.bus_out(bus_in),
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.int_tx_cmpl(int_tx_cmpl),
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.int_rx_cmpl(int_rx_cmpl),
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.int_tx_rst(int_tx_rst),
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.int_rx_rst(int_rx_rst),
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.scl(scl),
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.sda(sda)
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);
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endmodule
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