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-------------------------------------------------------------------------------
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-- This file is part of the project avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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-- description:
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-- AddRoundKey module for AES algorithm, basically a simple XOR for states and
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-- keyblocks.... just a simple XOR wrapped into a component for nicer usage.
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--
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--
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-------------------------------------------------------------------------------
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-- Author(s):
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-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Thomas Ruschival
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- * Neither the name of the nor the names of its contributors
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-- may be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-- version management:
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-- $Author$
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-- $Date$
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-- $Revision$
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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library avs_aes_lib;
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use avs_aes_lib.avs_aes_pkg.all;
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entity AddRoundKey is
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port (
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roundkey : in KEYBLOCK; -- Roundkey
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cypherblock : in STATE; -- State for this round
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result : out STATE); -- result
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end entity AddRoundKey;
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architecture arch1 of AddRoundKey is
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begin -- architecture arch1
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-- purpose: Adding (Xor) roundkey words with Keywords
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-- type : combinational
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-- inputs : cypherblock, roundkey
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-- outputs: result
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Xoring : process (cypherblock, roundkey) is
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begin -- process Xoring
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for cnt in cypherblock'range loop
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result(cnt) <= cypherblock(cnt) xor roundkey(cnt);
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end loop; -- cnt
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end process Xoring;
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end architecture arch1;
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