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--------------------------------------------------------------------------------
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-- This file is part of the project avs_aes
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-- see: http://opencores.org/project,avs_aes
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--
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-- description: Mux2, 2-Port-N-Bit Bit Mulitplexer
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--
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-------------------------------------------------------------------------------
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--
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-- Author(s):
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-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
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--
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--------------------------------------------------------------------------------
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-- Copyright (c) 2009, Authors and opencores.org
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright notice,
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-- this list of conditions and the following disclaimer in the documentation
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-- and/or other materials provided with the distribution.
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-- * Neither the name of the organization nor the names of its contributors
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-- may be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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-- THE POSSIBILITY OF SUCH DAMAGE
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-------------------------------------------------------------------------------
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-- version management:
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-- $Author$
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-- $Date$
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-- $Revision$
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity mux2 is
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generic (
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IOwidth : POSITIVE := 32 -- width of I/O ports
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);
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port (
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inport_a : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 1
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inport_b : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 2
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selector : in STD_LOGIC; -- switch to select ports
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outport : out STD_LOGIC_VECTOR (IOwidth-1 downto 0) -- output
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);
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end mux2;
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architecture arch1 of mux2 is
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begin -- arch1
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-- purpose: switch the ports
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-- type : combinational
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-- inputs : selector,inport_a,inport_b
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-- outputs: outport
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muxing : process (inport_a, inport_b, selector)
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begin -- PROCESS selector
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-- default behaviour to avoid latch
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outport <= inport_a;
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case selector is
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when '0' =>
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outport <= inport_a;
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when '1' =>
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outport <= inport_b;
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when others =>
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--pragma synthesis_off
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report "!! selector in arch1 of mux2 has strange value !!" severity warning;
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--pragma synthesis_on
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end case;
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end process muxing;
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end arch1;
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