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[/] [ax4lbr/] [trunk/] [rtl/] [axil2ipb.vhd] - Diff between revs 2 and 4

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Rev 2 Rev 4
Line 84... Line 84... 
    S_AXI_RREADY  : in  std_logic;
 
    S_AXI_RREADY  : in  std_logic;
 
    -- Write Response Channel
 
    -- Write Response Channel
 
    S_AXI_BRESP   : out std_logic_vector(1 downto 0);
 
    S_AXI_BRESP   : out std_logic_vector(1 downto 0);
 
    S_AXI_BVALID  : out std_logic;
 
    S_AXI_BVALID  : out std_logic;
 
    S_AXI_BREADY  : in  std_logic;
 
    S_AXI_BREADY  : in  std_logic;
 
 
 
    -- AWPROT and ARPROT - required by Altera
 
 
 
    --S_AXI_ARPROT  : in  std_logic_vector(2 downto 0);
 
 
 
    --S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
 
    -- Here we have the IPbus ports
 
    -- Here we have the IPbus ports
 
    ipb_clk       : out std_logic;
 
    ipb_clk       : out std_logic;
 
    ipb_rst       : out std_logic;
 
    ipb_rst       : out std_logic;
 
    -- master_ipb_out - flattened due to Vivado inability to handle user types
 
    -- master_ipb_out - flattened due to Vivado inability to handle user types
 
    -- in BD
 
    -- in BD

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