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https://opencores.org/ocsvn/ax4lbr/ax4lbr/trunk
[/] [ax4lbr/] [trunk/] [rtl/] [axil2wb.vhd] - Diff between revs 3 and 4
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| Rev 3 |
Rev 4 |
| Line 79... |
Line 79... |
S_AXI_RREADY : in std_logic;
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S_AXI_RREADY : in std_logic;
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-- Write Response Channel
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-- Write Response Channel
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BVALID : out std_logic;
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S_AXI_BVALID : out std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_BREADY : in std_logic;
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-- AWPROT and ARPROT - required by Altera
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--S_AXI_ARPROT : in std_logic_vector(2 downto 0);
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--S_AXI_AWPROT : in std_logic_vector(2 downto 0);
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-- Here we have the WB ports
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-- Here we have the WB ports
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-- The clock and reset are comming from AXI!
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-- The clock and reset are comming from AXI!
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wb_clk_o : out std_logic;
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wb_clk_o : out std_logic;
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wb_rst_o : out std_logic;
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wb_rst_o : out std_logic;
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-- master_ipb_out - flattened due to Vivado inability to handle user types
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-- master_ipb_out - flattened due to Vivado inability to handle user types
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