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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;
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library tauhop; use tauhop.axiTransactor.all;
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--/* TODO remove once generic packages are supported. */
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--/* TODO remove once generic packages are supported. */
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--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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entity axiBfmMaster is --generic(constant maxTransactions:positive);
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entity axiBfmMaster is --generic(constant maxTransactions:positive);
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port(aclk,n_areset:in std_ulogic;
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port(aclk,n_areset:in std_ulogic;
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/* BFM signalling. */
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/* BFM signalling. */
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readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); -- this is tauhop.transactor.t_bfm.
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/* FIXME Generic package defect. ModelSim currently can't make tauhop.axiTransactor.i_transactor visible. */
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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readRequest,writeRequest:in i_transactor.t_bfm:=((others=>'X'),(others=>'X'),false);
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--readRequest,writeRequest:in i_transactor.t_bfm:=((others=>'X'),(others=>'X'),false);
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readResponse,writeResponse:buffer i_transactor.t_bfm; -- use buffer until synthesis tools support reading from out ports.
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/* AXI Master interface */
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/* AXI Master interface */
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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symbolsPerTransfer:in t_cnt;
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symbolsPerTransfer:in i_transactor.t_cnt;
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outstandingTransactions:buffer t_cnt
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outstandingTransactions:buffer i_transactor.t_cnt
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/* Debug ports. */
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/* Debug ports. */
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
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-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
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architecture rtl of axiBfmMaster is
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architecture rtl of axiBfmMaster is
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/* Finite-state Machines. */
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/* Finite-state Machines. */
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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/* BFM signalling. */
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/* BFM signalling. */
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signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readResponse,i_writeResponse:t_bfm;
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signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
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begin
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begin
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/* Transaction counter. */
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/* Transaction counter. */
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process(n_areset,symbolsPerTransfer,aclk) is begin
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process(n_areset,symbolsPerTransfer,aclk) is begin
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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