Line 53... |
Line 53... |
|
|
-- /* AXI Slave interface */
|
-- /* AXI Slave interface */
|
-- axiSlave_in:in tAxi4Transactor_m2s;
|
-- axiSlave_in:in tAxi4Transactor_m2s;
|
-- axiSlave_out:buffer tAxi4Transactor_s2m;
|
-- axiSlave_out:buffer tAxi4Transactor_s2m;
|
|
|
-- symbolsPerTransfer:in i_transactor.t_cnt;
|
|
-- outstandingTransactions:in i_transactor.t_cnt;
|
|
lastTransaction:in boolean;
|
lastTransaction:in boolean;
|
|
|
/* Debug ports. */
|
/* Debug ports. */
|
-- dbg_cnt:out unsigned(9 downto 0);
|
-- dbg_cnt:out unsigned(9 downto 0);
|
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
|
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
|
Line 72... |
Line 70... |
|
|
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
|
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
|
signal i_trigger,trigger:boolean;
|
signal i_trigger,trigger:boolean;
|
|
|
/* BFM signalling. */
|
/* BFM signalling. */
|
-- signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
|
|
-- signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
|
|
signal i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
|
signal i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
|
signal i_writeResponse:i_transactor.t_bfm;
|
signal i_writeResponse:i_transactor.t_bfm;
|
|
|
begin
|
begin
|
i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
|
i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
|
Line 92... |
Line 88... |
when idle=>
|
when idle=>
|
if i_trigger then axiTxState<=payload; end if;
|
if i_trigger then axiTxState<=payload; end if;
|
when payload=>
|
when payload=>
|
if lastTransaction then axiTxState<=endOfTx; end if;
|
if lastTransaction then axiTxState<=endOfTx; end if;
|
when endOfTx=>
|
when endOfTx=>
|
axiTxState<=idle;
|
if axiMaster_in.tReady then axiTxState<=idle; end if;
|
when others=>axiTxState<=idle;
|
when others=>axiTxState<=idle;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process axi_bfmTx_ns;
|
end process axi_bfmTx_ns;
|
|
|
/* output logic for AXI4-Stream Master Tx BFM. */
|
/* output logic for AXI4-Stream Master Tx BFM. */
|
axi_bfmTx_op: process(all) is begin
|
axi_bfmTx_op: process(all) is begin
|
i_writeResponse<=writeResponse;
|
i_writeResponse<=writeResponse;
|
|
|
|
i_axiMaster_out<=axiMaster_out;
|
i_axiMaster_out.tLast<=false;
|
i_axiMaster_out.tLast<=false;
|
i_writeResponse.trigger<=false;
|
i_writeResponse.trigger<=false;
|
|
|
case next_axiTxState is
|
case next_axiTxState is
|
when idle=>
|
when idle=>
|
Line 131... |
Line 128... |
end case;
|
end case;
|
end process axi_bfmTx_op;
|
end process axi_bfmTx_op;
|
|
|
/* state registers and pipelines for AXI4-Stream Tx BFM. */
|
/* state registers and pipelines for AXI4-Stream Tx BFM. */
|
process(aclk) is begin
|
process(aclk) is begin
|
if falling_edge(aclk) then
|
if rising_edge(aclk) or falling_edge(aclk) then
|
next_axiTxState<=axiTxState;
|
next_axiTxState<=axiTxState;
|
i_writeRequest<=writeRequest;
|
i_writeRequest<=writeRequest;
|
writeResponse<=i_writeResponse;
|
writeResponse<=i_writeResponse;
|
axiMaster_out<=i_axiMaster_out;
|
axiMaster_out<=i_axiMaster_out;
|
trigger<=i_trigger;
|
trigger<=i_trigger;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
/*
|
|
fastPipelines: entity work.ddr(rtl) generic map(busWidth=>8)
|
|
port map(reset=>reset,
|
|
clk=>aclk,
|
|
d=>next_axiTxState,
|
|
q=>axiTxState
|
|
);
|
|
*/
|
|
|
dbg_axiTxFSM<=axiTxState;
|
dbg_axiTxFSM<=axiTxState;
|
end architecture rtl;
|
end architecture rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|