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https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk
[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [axi4-stream-bfm-master.vhdl] - Diff between revs 7 and 8
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| Rev 7 |
Rev 8 |
| Line 57... |
Line 57... |
-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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symbolsPerTransfer:in t_cnt;
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symbolsPerTransfer:in t_cnt;
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outstandingTransactions:out t_cnt;
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outstandingTransactions:out t_cnt
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/* Debug ports. */
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/* Debug ports. */
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dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
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);
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);
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end entity axiBfmMaster;
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end entity axiBfmMaster;
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architecture rtl of axiBfmMaster is
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architecture rtl of axiBfmMaster is
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/* Finite-state Machines. */
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/* Finite-state Machines. */
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| Line 133... |
Line 133... |
i_axiMaster_out<=axiMaster_out;
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i_axiMaster_out<=axiMaster_out;
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i_writeRequest<=writeRequest;
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i_writeRequest<=writeRequest;
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end if;
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end if;
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end process;
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end process;
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dbg_axiTxFsm<=axiTxState;
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-- dbg_axiTxFsm<=axiTxState;
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end architecture rtl;
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end architecture rtl;
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