| Line 81... |
Line 81... |
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signal response,i_response:boolean;
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signal response,i_response:boolean;
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begin
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begin
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/* Transaction counter. */
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/* Transaction counter. */
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process(n_areset,aclk) is begin
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process(n_areset,symbolsPerTransfer,aclk) is begin
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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elsif rising_edge(aclk) then
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elsif rising_edge(aclk) then
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if outstandingTransactions>0 then outstandingTransactions<=outstandingTransactions-1;
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if outstandingTransactions>0 then outstandingTransactions<=outstandingTransactions-1;
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else
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else
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outstandingTransactions<=symbolsPerTransfer;
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outstandingTransactions<=symbolsPerTransfer;
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| Line 116... |
Line 116... |
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case next_axiTxState is
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case next_axiTxState is
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when payload=>
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when payload=>
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axiMaster_out.tValid<=true;
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axiMaster_out.tValid<=true;
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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axiMaster_out.tData<=writeRequest.message; --TODO: writeRequest.message should change every aclk cycle.
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axiMaster_out.tData<=writeRequest.message;
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end if;
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end if;
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when others=> axiMaster_out.tValid<=false; axiMaster_out.tData<=(others=>'Z'); --TODO: set 'Z' to '0' for synthesis.
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when others=> axiMaster_out.tValid<=false; axiMaster_out.tData<=(others=>'Z'); --TODO: set 'Z' to '0' for synthesis.
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end case;
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end case;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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| Line 135... |
Line 135... |
end if;
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end if;
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end process;
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end process;
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-- dbg_axiTxFsm<=axiTxState;
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-- dbg_axiTxFsm<=axiTxState;
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end architecture rtl;
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end architecture rtl;
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