| Line 53... |
Line 53... |
-- subtype t_qualifier is std_ulogic_vector(32/8-1 downto 0);
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-- subtype t_qualifier is std_ulogic_vector(32/8-1 downto 0);
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-- subtype t_id is unsigned(31 downto 0);
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-- subtype t_id is unsigned(31 downto 0);
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-- subtype t_resp is unsigned(1 downto 0); --2 bits. b"00" = OKAY, b"01" = ExOKAY, b"10" = SLVERR (slave error), b"11" = DECERR (decode error).
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-- subtype t_resp is unsigned(1 downto 0); --2 bits. b"00" = OKAY, b"01" = ExOKAY, b"10" = SLVERR (slave error), b"11" = DECERR (decode error).
|
|
|
/* AXI Transactor block interfaces. */
|
/* AXI Transactor block interfaces. */
|
type tAxi4Transactor_m2s is record
|
type t_axi4Transactor_m2s is record
|
/* Address must be unresolved, because you need to drive the read address only when read is asserted, and
|
/* Address must be unresolved, because you need to drive the read address only when read is asserted, and
|
drive the write address when write is asserted. Resolution functions are not expected to know how to decide this.
|
drive the write address when write is asserted. Resolution functions are not expected to know how to decide this.
|
*/
|
*/
|
/* Write address channel. */
|
/* Write address channel. */
|
awId:t_id;
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awId:t_id;
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| Line 102... |
Line 102... |
arAddr:t_addr;
|
arAddr:t_addr;
|
arProt:boolean;
|
arProt:boolean;
|
|
|
/* Read data channel. */
|
/* Read data channel. */
|
rReady:boolean;
|
rReady:boolean;
|
end record tAxi4Transactor_m2s;
|
end record t_axi4Transactor_m2s;
|
|
|
type tAxi4Transactor_s2m is record
|
type t_axi4Transactor_s2m is record
|
/* Write address channel. */
|
/* Write address channel. */
|
awReady:boolean;
|
awReady:boolean;
|
|
|
/* Write data channel. */
|
/* Write data channel. */
|
wReady:boolean;
|
wReady:boolean;
|
| Line 129... |
Line 129... |
-- rUser:
|
-- rUser:
|
-- AXI4-Lite required signals.
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-- AXI4-Lite required signals.
|
rValid:boolean;
|
rValid:boolean;
|
rData:t_msg;
|
rData:t_msg;
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rResp:t_resp;
|
rResp:t_resp;
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end record tAxi4Transactor_s2m;
|
end record t_axi4Transactor_s2m;
|
|
|
type tAxi4StreamTransactor_m2s is record
|
type t_axi4StreamTransactor_m2s is record
|
/* AXI4 streaming interface. */
|
/* AXI4 streaming interface. */
|
tValid:boolean;
|
tValid:boolean;
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tData:t_msg;
|
tData:t_msg;
|
tStrb:t_qualifier;
|
tStrb:t_qualifier;
|
tKeep:t_qualifier;
|
tKeep:t_qualifier;
|
tLast:boolean;
|
tLast:boolean;
|
tId:t_id;
|
tId:t_id;
|
tDest:t_dest;
|
tDest:t_dest;
|
tUser:t_user;
|
tUser:t_user;
|
end record tAxi4StreamTransactor_m2s;
|
end record t_axi4StreamTransactor_m2s;
|
|
|
type tAxi4StreamTransactor_s2m is record
|
type t_axi4StreamTransactor_s2m is record
|
tReady:boolean;
|
tReady:boolean;
|
end record tAxi4StreamTransactor_s2m;
|
end record t_axi4StreamTransactor_s2m;
|
|
|
-- /* AXI Low-power interface. */
|
-- /* AXI Low-power interface. */
|
-- type tAxiTransactor_lp is record
|
-- type tAxiTransactor_lp is record
|
-- cSysReq:
|
-- cSysReq:
|
-- cSysAck:
|
-- cSysAck:
|
