| Line 76... |
Line 76... |
signal i_readResponse,i_writeResponse:t_bfm;
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signal i_readResponse,i_writeResponse:t_bfm;
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begin
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begin
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/* Transaction counter. */
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/* Transaction counter. */
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process(n_areset,symbolsPerTransfer,aclk) is begin
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process(n_areset,symbolsPerTransfer,aclk) is begin
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/* Using synchronous reset will meet timing. However, because outstandingTransactions is a huge
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--if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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register set, using asynchronous reset will violate timing.
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if falling_edge(aclk) then
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FIXME Try and close timing even with asynchronous reset applied on outstandingTransactions.
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/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
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Using asynchronous reset will help to lower power.
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*/
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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elsif falling_edge(aclk) then
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else
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if outstandingTransactions<1 then
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if outstandingTransactions<1 then
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outstandingTransactions<=symbolsPerTransfer;
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_ns: process(all) is begin
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axi_bfmTx_ns: process(all) is begin
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axiTxState<=next_axiTxState;
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axiTxState<=next_axiTxState;
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| Line 123... |
Line 122... |
if writeRequest.trigger xor i_writeRequest.trigger then
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if writeRequest.trigger xor i_writeRequest.trigger then
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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axiMaster_out.tValid<=true;
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end if;
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end if;
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if not n_areset then axiMaster_out.tData<=(others=>'Z');
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else
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case next_axiTxState is
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case next_axiTxState is
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when payload=>
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when payload=>
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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axiMaster_out.tValid<=true;
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| Line 136... |
Line 137... |
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
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if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end if;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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process(n_areset,aclk) is begin
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process(n_areset,aclk) is begin
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if falling_edge(aclk) then
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if falling_edge(aclk) then
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