| Line 54... |
Line 54... |
-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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symbolsPerTransfer:in t_cnt;
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symbolsPerTransfer:in t_cnt;
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outstandingTransactions:buffer t_cnt;
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outstandingTransactions:in t_cnt;
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/* Debug ports. */
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/* Debug ports. */
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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| Line 74... |
Line 74... |
signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readResponse,i_writeResponse:t_bfm;
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signal i_readResponse,i_writeResponse:t_bfm;
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begin
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begin
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/* Transaction counter. */
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process(n_areset,symbolsPerTransfer,aclk) is begin
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--if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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if falling_edge(aclk) then
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/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
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if not n_areset then outstandingTransactions<=symbolsPerTransfer;
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else
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if outstandingTransactions<1 then
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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end if;
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end process;
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_ns: process(all) is begin
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axi_bfmTx_ns: process(all) is begin
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axiTxState<=next_axiTxState;
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axiTxState<=next_axiTxState;
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if not n_areset then axiTxState<=idle;
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if not n_areset then axiTxState<=idle;
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