| Line 36... |
Line 36... |
from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
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--library tauhop; use tauhop.axiTransactor.all;
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--library tauhop; use tauhop.axiTransactor.all;
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--/* TODO remove once generic packages are supported. */
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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entity axiBfmMaster is
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entity axiBfmMaster is
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port(aclk,n_areset:in std_ulogic;
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port(aclk,n_areset:in std_ulogic;
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/* BFM signalling. */
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/* BFM signalling. */
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readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false);
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readRequest,writeRequest:in t_bfm:=(address=>(others=>'X'), message=>(others=>'X'), trigger=>false);
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
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/* AXI Master interface */
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/* AXI Master interface */
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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| Line 67... |
Line 67... |
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architecture rtl of axiBfmMaster is
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architecture rtl of axiBfmMaster is
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/* Finite-state Machines. */
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/* Finite-state Machines. */
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
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/* BFM signalling. */
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signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
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signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_trigger,trigger:boolean;
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signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal i_readResponse,i_writeResponse:t_bfm;
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/* BFM signalling. */
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-- signal i_readRequest,i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- signal i_readResponse,i_writeResponse:t_bfm;
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signal i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal i_writeResponse:t_bfm;
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begin
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begin
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i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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/* next-state logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_ns: process(all) is begin
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axi_bfmTx_ns: process(all) is begin
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axiTxState<=next_axiTxState;
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axiTxState<=next_axiTxState;
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if not n_areset then axiTxState<=idle;
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if not n_areset then axiTxState<=idle;
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else
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else
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
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if i_trigger then axiTxState<=payload; end if;
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when payload=>
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when payload=>
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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when endOfTx=>
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when endOfTx=>
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axiTxState<=idle;
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axiTxState<=idle;
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when others=>axiTxState<=idle;
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when others=>axiTxState<=idle;
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Line 101... |
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/* output logic for AXI4-Stream Master Tx BFM. */
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/* output logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_op: process(all) is begin
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axi_bfmTx_op: process(all) is begin
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i_writeResponse<=writeResponse;
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i_writeResponse<=writeResponse;
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axiMaster_out.tValid<=false;
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i_axiMaster_out.tValid<=false;
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axiMaster_out.tLast<=false;
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i_axiMaster_out.tLast<=false;
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axiMaster_out.tData<=(others=>'Z');
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i_axiMaster_out.tData<=(others=>'Z');
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i_writeResponse.trigger<=false;
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i_writeResponse.trigger<=false;
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if writeRequest.trigger xor i_writeRequest.trigger then
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axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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end if;
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if not n_areset then axiMaster_out.tData<=(others=>'Z');
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else
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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if i_trigger then
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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end if;
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when payload=>
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when payload=>
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axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tData<=writeRequest.message;
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axiMaster_out.tValid<=true;
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i_axiMaster_out.tValid<=true;
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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i_writeResponse.trigger<=true;
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i_writeResponse.trigger<=true;
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end if;
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end if;
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/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
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if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
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if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end if;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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process(n_areset,aclk) is begin
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process(aclk) is begin
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if falling_edge(aclk) then
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if falling_edge(aclk) then
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next_axiTxState<=axiTxState;
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next_axiTxState<=axiTxState;
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i_writeRequest<=writeRequest;
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i_writeRequest<=writeRequest;
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end if;
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end process;
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process(aclk) is begin
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if rising_edge(aclk) then
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writeResponse<=i_writeResponse;
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writeResponse<=i_writeResponse;
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axiMaster_out<=i_axiMaster_out;
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trigger<=i_trigger;
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end if;
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end if;
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end process;
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end process;
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dbg_axiTxFSM<=axiTxState;
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dbg_axiTxFSM<=axiTxState;
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end architecture rtl;
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end architecture rtl;
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