| Line 53... |
Line 53... |
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-- /* AXI Slave interface */
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-- /* AXI Slave interface */
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_in:in tAxi4Transactor_m2s;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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-- axiSlave_out:buffer tAxi4Transactor_s2m;
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symbolsPerTransfer:in t_cnt;
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lastTransaction:in boolean;
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outstandingTransactions:in t_cnt;
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/* Debug ports. */
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/* Debug ports. */
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_cnt:out unsigned(9 downto 0);
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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dbg_axiTxFsm:out axiBfmStatesTx:=idle
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| Line 89... |
Line 88... |
else
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else
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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if i_trigger then axiTxState<=payload; end if;
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if i_trigger then axiTxState<=payload; end if;
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when payload=>
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when payload=>
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if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
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if lastTransaction then axiTxState<=endOfTx; end if;
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when endOfTx=>
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when endOfTx=>
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axiTxState<=idle;
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axiTxState<=idle;
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when others=>axiTxState<=idle;
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when others=>axiTxState<=idle;
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end case;
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end case;
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end if;
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end if;
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Line 100... |
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/* output logic for AXI4-Stream Master Tx BFM. */
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/* output logic for AXI4-Stream Master Tx BFM. */
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axi_bfmTx_op: process(all) is begin
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axi_bfmTx_op: process(all) is begin
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i_writeResponse<=writeResponse;
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i_writeResponse<=writeResponse;
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i_axiMaster_out.tValid<=false;
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i_axiMaster_out<=axiMaster_out;
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i_axiMaster_out.tLast<=false;
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i_axiMaster_out.tLast<=false;
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i_axiMaster_out.tData<=(others=>'Z');
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i_writeResponse.trigger<=false;
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i_writeResponse.trigger<=false;
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case next_axiTxState is
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case next_axiTxState is
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when idle=>
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when idle=>
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i_axiMaster_out.tValid<=false;
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i_axiMaster_out.tData<=(others=>'Z');
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if i_trigger then
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if i_trigger then
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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i_axiMaster_out.tValid<=true;
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end if;
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end if;
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when payload=>
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when payload | endOfTx =>
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if i_trigger then
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tData<=writeRequest.message;
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i_axiMaster_out.tValid<=true;
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i_axiMaster_out.tValid<=true;
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end if;
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if axiMaster_in.tReady then
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if axiMaster_in.tReady then
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i_writeResponse.trigger<=true;
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i_writeResponse.trigger<=true;
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end if;
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end if;
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if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
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if lastTransaction then i_axiMaster_out.tLast<=true; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end process axi_bfmTx_op;
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end process axi_bfmTx_op;
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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/* state registers and pipelines for AXI4-Stream Tx BFM. */
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