| Line 90... |
Line 90... |
signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity work.axiBfmMaster(rtl)
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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port map(
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port map(
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aclk=>irq_write, n_areset=>not reset,
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aclk=>irq_write, n_areset=>not reset,
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|
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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| Line 110... |
Line 110... |
irq_write<=clk when not reset else '0';
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irq_write<=clk when not reset else '0';
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/* Simulation Tester. */
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/* Simulation Tester. */
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/* PLL to generate tester's clock. */
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/* PLL to generate tester's clock. */
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f100MHz: entity altera.pll(syn) port map(
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f100MHz: entity altera.pll(syn) port map(
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areset=>'0', --not reset, --not nReset,
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areset=>'0', --not nReset,
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inclk0=>clk,
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inclk0=>clk,
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c0=>testerClk,
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c0=>testerClk,
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locked=>open
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locked=>open
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);
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);
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| Line 140... |
Line 140... |
if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
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if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
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end if;
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end if;
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end process por;
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end process por;
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when reset else '0';
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anlysr_trigger<='1' when reset else '0';
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|
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/* Disable this for synthesis as this is not currently synthesisable.
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/* Disable this for synthesis as this is not currently synthesisable.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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*/
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*/
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/* synthesis translate_off */
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/* synthesis translate_off */
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| Line 172... |
Line 172... |
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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/* Simulate only if you have compiled Altera's simulation libraries. */
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/* Simulate only if you have compiled Altera's simulation libraries. */
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i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
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i_bist_logicAnalyser: entity altera.stp(syn) port map(
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acq_clk=>testerClk,
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acq_clk=>testerClk,
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acq_data_in=>anlysr_dataIn,
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acq_data_in=>anlysr_dataIn,
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acq_trigger_in=>"1",
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acq_trigger_in=>"1",
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trigger_in=>anlysr_trigger
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trigger_in=>anlysr_trigger
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);
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);
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