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library altera; use altera.stp;
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library altera; use altera.stp;
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entity user is port(
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entity user is port(
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/* Comment-out for simulation. */
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/* Comment-out for simulation. */
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clk,nReset:in std_ulogic;
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clk,reset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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/* Debug ports. */
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/* Debug ports. */
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selTxn:in unsigned(3 downto 0):=x"0"
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);
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);
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end entity user;
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end entity user;
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architecture rtl of user is
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architecture rtl of user is
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signal i_reset:std_ulogic:='0';
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signal porCnt:unsigned(3 downto 0);
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/* Global counters. */
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/* Global counters. */
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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signal symbolsPerTransfer:t_cnt;
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signal symbolsPerTransfer:t_cnt;
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signal outstandingTransactions:t_cnt;
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signal outstandingTransactions:t_cnt;
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/* BFM signalling. */
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/* BFM signalling. */
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signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
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signal readResponse,writeResponse:t_bfm;
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signal readResponse:t_bfm;
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signal writeResponse:t_bfm;
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,reset:std_ulogic:='0';
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signal clk,reset:std_ulogic:='0';
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attribute period:time; attribute period of clk:signal is 10 ps;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal cnt:unsigned(3 downto 0);
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signal reset:std_ulogic:='0';
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signal testerClk:std_ulogic;
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--signal trigger:boolean;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(127 downto 0);
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signal anlysr_dataIn:std_logic_vector(255 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal anlysr_trigger:std_ulogic;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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port map(
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port map(
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aclk=>irq_write, n_areset=>not reset,
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aclk=>irq_write, n_areset=>not i_reset,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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| Line 104... |
Line 100... |
symbolsPerTransfer=>symbolsPerTransfer,
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symbolsPerTransfer=>symbolsPerTransfer,
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outstandingTransactions=>outstandingTransactions,
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outstandingTransactions=>outstandingTransactions,
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dbg_axiTxFSM=>dbg_axiTxFSM
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dbg_axiTxFSM=>dbg_axiTxFSM
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);
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);
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/* Interrupt-request generator. */
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/* Clocks and reset. */
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irq_write<=clk when not reset else '0';
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/* Power-on Reset circuitry. */
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por: process(reset,clk) is begin
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/* Simulation Tester. */
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if reset then i_reset<='1'; porCnt<=(others=>'1');
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/* PLL to generate tester's clock. */
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f100MHz: entity altera.pll(syn) port map(
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areset=>'0', --not nReset,
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inclk0=>clk,
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c0=>testerClk,
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locked=>open
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);
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/* synthesis translate_off */
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clk<=not clk after 10 ps;
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process is begin
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nReset<='1'; wait for 1 ps;
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nReset<='0'; wait for 500 ps;
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nReset<='1';
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wait;
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end process;
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/* synthesis translate_on */
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/* Hardware tester. */
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por: process(nReset,clk) is
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--variable cnt:unsigned(7 downto 0):=(others=>'1');
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begin
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if not nReset then cnt<=(others=>'1');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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reset<='0';
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i_reset<='0';
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if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
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if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
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end if;
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end if;
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end process por;
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end process por;
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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anlysr_trigger<='1' when reset else '0';
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/* Disable this for synthesis as this is not currently synthesisable.
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Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
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*/
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/* synthesis translate_off */
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--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
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/* synthesis translate_on */
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anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
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anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
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--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
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anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
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anlysr_dataIn(18)<='1' when clk else '0';
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anlysr_dataIn(19)<='1' when reset else '0';
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anlysr_dataIn(20)<='1' when irq_write else '0';
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anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
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anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
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anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
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anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
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anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
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anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
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anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
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anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
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--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
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anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt);
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anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
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/* Simulate only if you have compiled Altera's simulation libraries. */
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i_bist_logicAnalyser: entity altera.stp(syn) port map(
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acq_clk=>testerClk,
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acq_data_in=>anlysr_dataIn,
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acq_trigger_in=>"1",
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trigger_in=>anlysr_trigger
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);
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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*/
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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clk<=not clk after clk'period/2;
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process is begin
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process is begin
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/* Fast read. */
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reset<='0'; wait for 1 ps;
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while not axiMaster_out.tLast loop
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reset<='1'; wait for 500 ps;
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/* Wait for tValid to assert. */
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reset<='0';
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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end loop;
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wait until falling_edge(clk);
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/* Normal read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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end loop;
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for i in 0 to 10 loop
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wait until falling_edge(clk);
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end loop;
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/* One-shot read. */
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Synthesisable stimuli sequencer. */
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/* Simulation Tester. */
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process(clk) is begin
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if falling_edge(clk) then
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axiMaster_in.tReady<=false;
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--if axiMaster_out.tValid and not axiMaster_out.tLast then
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if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
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axiMaster_in.tReady<=true;
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end if;
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end if;
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end process;
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/* Data transmitter. */
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sequencer_ns: process(all) is begin
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txFSM<=i_txFSM;
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if reset then txFSM<=idle;
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else
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case i_txFSM is
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when idle=>
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if outstandingTransactions>0 then txFSM<=transmitting; end if;
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when transmitting=>
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if axiMaster_out.tLast then
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txFSM<=idle;
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end if;
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when others=> null;
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end case;
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end if;
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end process sequencer_ns;
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/* Data transmitter. */
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sequencer_op: process(reset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in t_addr) is begin
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read(readRequest,address);
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end procedure read;
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procedure write(data:in t_msg) is begin
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write(request=>writeRequest, address=>(others=>'-'), data=>data);
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end procedure write;
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variable isPktError:boolean;
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/* Tester variables. */
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/* Synthesis-only randomisation. */
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variable rand0:signed(axiMaster_out.tData'high downto 0);
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/* Simulation-only randomisation. */
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/* synthesis translate_off */
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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if reset then
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/* synthesis only. */
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rand0:=(others=>'0');
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/* simulation only. */
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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/* synthesis translate_on */
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--txFSM<=idle;
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elsif falling_edge(irq_write) then
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case txFSM is
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when transmitting=>
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if txFSM/=i_txFSM or writeResponse.trigger then
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/* synthesis translate_off */
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write(rv0.RandSigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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write(rand0);
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rand0:=rand0+1;
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end if;
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when others=>null;
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end case;
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end if;
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end process sequencer_op;
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sequencer_regs: process(irq_write) is begin
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if falling_edge(irq_write) then
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i_txFSM<=txFSM;
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end if;
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end process sequencer_regs;
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/* Transaction counter. */
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process(nReset,symbolsPerTransfer,irq_write) is begin
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if not nReset then outstandingTransactions<=symbolsPerTransfer;
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elsif falling_edge(irq_write) then
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/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
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if not nReset then outstandingTransactions<=symbolsPerTransfer;
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else
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if outstandingTransactions<1 then
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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end if;
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end process;
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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process(reset,irq_write) is
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/* synthesis translate_off */
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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if reset then
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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symbolsPerTransfer<=128x"8";
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elsif rising_edge(irq_write) then
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if axiMaster_out.tLast then
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/* synthesis only. */
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/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
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--symbolsPerTransfer<=(others=>'0');
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/* Testcase 2: number of symbols per transfer is randomised. */
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--uniform(seed0,seed1,rand0);
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--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
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--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
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/* synthesis translate_off */
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
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/* Hardware tester. */
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end if;
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bist: entity work.tester(rtl) port map(
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end if;
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clk=>clk, reset=>i_reset,
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end process;
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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irq_write=>irq_write,
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symbolsPerTransfer=>symbolsPerTransfer,
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outstandingTransactions=>outstandingTransactions,
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selTxn=>selTxn
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);
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end architecture rtl;
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end architecture rtl;
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No newline at end of file
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No newline at end of file
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