| Line 57... |
Line 57... |
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
|
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
|
signal symbolsPerTransfer:t_cnt;
|
signal symbolsPerTransfer:t_cnt;
|
signal outstandingTransactions:t_cnt;
|
signal outstandingTransactions:t_cnt;
|
|
|
/* BFM signalling. */
|
/* BFM signalling. */
|
signal readRequest,next_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
|
signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
|
signal writeRequest,next_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
|
signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
|
signal readResponse,next_readResponse:t_bfm;
|
signal readResponse:t_bfm;
|
signal writeResponse,next_writeResponse:t_bfm;
|
signal writeResponse:t_bfm;
|
|
|
|
type txStates is (idle,transmitting);
|
|
signal txFSM,i_txFSM:txStates;
|
|
--signal response,i_response:boolean;
|
|
|
/* Tester signals. */
|
/* Tester signals. */
|
/* synthesis translate_off */
|
/* synthesis translate_off */
|
signal clk,reset:std_ulogic:='0';
|
signal clk,reset:std_ulogic:='0';
|
signal axiMaster_in:t_axi4StreamTransactor_s2m;
|
signal axiMaster_in:t_axi4StreamTransactor_s2m;
|
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
signal irq_write:std_ulogic; -- clock gating.
|
signal irq_write:std_ulogic; -- clock gating.
|
|
|
begin
|
begin
|
/* pipelines. */
|
|
process(clk) is begin
|
|
if rising_edge(clk) then
|
|
next_readRequest<=readRequest;
|
|
next_writeRequest<=writeRequest;
|
|
next_readResponse<=readResponse;
|
|
next_writeResponse<=writeResponse;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
/* Bus functional models. */
|
/* Bus functional models. */
|
axiMaster: entity work.axiBfmMaster(rtl)
|
axiMaster: entity work.axiBfmMaster(rtl)
|
-- generic map(maxTransactions=>maxSymbols)
|
|
port map(
|
port map(
|
aclk=>irq_write, n_areset=>not reset,
|
aclk=>irq_write, n_areset=>not reset,
|
trigger=>irq_write='1',
|
|
|
|
readRequest=>readRequest, writeRequest=>writeRequest,
|
readRequest=>readRequest, writeRequest=>writeRequest,
|
readResponse=>readResponse, writeResponse=>writeResponse,
|
readResponse=>readResponse, writeResponse=>writeResponse,
|
axiMaster_in=>axiMaster_in,
|
axiMaster_in=>axiMaster_in,
|
axiMaster_out=>axiMaster_out,
|
axiMaster_out=>axiMaster_out,
|
| Line 116... |
Line 106... |
/* synthesis translate_on */
|
/* synthesis translate_on */
|
|
|
/* Hardware tester. */
|
/* Hardware tester. */
|
|
|
|
|
/* Stimuli sequencer. */
|
/* Stimuli sequencer. TODO move to tester/stimuli.
|
axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
|
This emulates the AXI4-Stream Slave.
|
|
*/
|
|
/* synthesis translate_off */
|
|
process is begin
|
|
/* Fast read. */
|
|
while not axiMaster_out.tLast loop
|
|
/* Wait for tValid to assert. */
|
|
while not axiMaster_out.tValid loop
|
|
wait until falling_edge(clk);
|
|
end loop;
|
|
|
|
axiMaster_in.tReady<=true;
|
|
|
|
wait until falling_edge(clk);
|
|
axiMaster_in.tReady<=false;
|
|
end loop;
|
|
|
|
wait until falling_edge(clk);
|
|
|
|
/* Normal read. */
|
|
while not axiMaster_out.tLast loop
|
|
/* Wait for tValid to assert. */
|
|
while not axiMaster_out.tValid loop
|
|
wait until falling_edge(clk);
|
|
end loop;
|
|
|
|
wait until falling_edge(clk);
|
|
axiMaster_in.tReady<=true;
|
|
|
|
wait until falling_edge(clk);
|
|
axiMaster_in.tReady<=false;
|
|
end loop;
|
|
|
|
for i in 0 to 10 loop
|
|
wait until falling_edge(clk);
|
|
end loop;
|
|
|
|
/* One-shot read. */
|
|
axiMaster_in.tReady<=true;
|
|
|
|
wait until falling_edge(clk);
|
|
axiMaster_in.tReady<=false;
|
|
|
|
wait;
|
|
end process;
|
|
/* synthesis translate_on */
|
|
|
|
/* Data transmitter. */
|
sequencer: process(reset,irq_write) is
|
sequencer: process(reset,irq_write) is
|
/* Local procedures to map BFM signals with the package procedure. */
|
/* Local procedures to map BFM signals with the package procedure. */
|
procedure read(address:in t_addr) is begin
|
procedure read(address:in t_addr) is begin
|
read(readRequest,address);
|
read(readRequest,address);
|
end procedure read;
|
end procedure read;
|
| Line 132... |
Line 168... |
end procedure write;
|
end procedure write;
|
|
|
variable isPktError:boolean;
|
variable isPktError:boolean;
|
|
|
/* Simulation-only randomisation. */
|
/* Simulation-only randomisation. */
|
variable rv0,rv1:RandomPType;
|
variable rv0:RandomPType;
|
-- variable seed0,seed1:positive:=1;
|
|
-- variable rand0:real;
|
|
|
|
begin
|
begin
|
if reset then
|
if reset then
|
-- seed0:=1; seed1:=1;
|
|
-- uniform(seed0,seed1,rand0);
|
|
--
|
|
-- symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8);
|
|
|
|
rv0.InitSeed(rv0'instance_name);
|
rv0.InitSeed(rv0'instance_name);
|
rv1.InitSeed(rv1'instance_name);
|
txFSM<=idle;
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
|
elsif falling_edge(irq_write) then
|
elsif falling_edge(irq_write) then
|
|
case txFSM is
|
|
when idle=>
|
if outstandingTransactions>0 then
|
if outstandingTransactions>0 then
|
-- uniform(seed0,seed1,rand0);
|
write(rv0.RandSigned(axiMaster_out.tData'length));
|
-- write(to_signed(integer(rand0 * 2.0**31),64));
|
txFSM<=transmitting;
|
|
end if;
|
|
when transmitting=>
|
|
if writeResponse.trigger then
|
|
write(rv0.RandSigned(axiMaster_out.tData'length));
|
|
end if;
|
|
|
write(rv1.RandSigned(axiMaster_out.tData'length));
|
if axiMaster_out.tLast then
|
else
|
txFSM<=idle;
|
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
|
end if;
|
--symbolsPerTransfer<=(others=>'0');
|
when others=>null;
|
|
end case;
|
/* Testcase 2: number of symbols per transfer is randomised. */
|
end if;
|
-- uniform(seed0,seed1,rand0);
|
end process sequencer;
|
-- symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
|
|
-- report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
|
|
|
|
/* Truncate symbolsPerTransfer to 8 bits, so that it uses a "small" value for simulation. */
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
|
|
process(reset,irq_write) is
|
|
variable rv0:RandomPType;
|
|
begin
|
|
if reset then
|
|
rv0.InitSeed(rv0'instance_name);
|
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
|
elsif rising_edge(irq_write) then
|
|
if axiMaster_out.tLast then
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
|
end if;
|
end if;
|
end if;
|
end if;
|
end process sequencer;
|
end process;
|
end architecture rtl;
|
end architecture rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
