| Line 34... |
Line 34... |
Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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/* synthesis translate_on */
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entity user is port(
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entity user is port(
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/* Comment-out for simulation. */
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/* Comment-out for simulation. */
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-- clk,reset:in std_ulogic;
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-- clk,nReset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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| Line 64... |
Line 68... |
signal readResponse:t_bfm;
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signal readResponse:t_bfm;
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signal writeResponse:t_bfm;
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signal writeResponse:t_bfm;
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type txStates is (idle,transmitting);
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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signal txFSM,i_txFSM:txStates;
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--signal response,i_response:boolean;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,reset:std_ulogic:='0';
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signal clk,nReset:std_ulogic:='0';
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity work.axiBfmMaster(rtl)
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axiMaster: entity work.axiBfmMaster(rtl)
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port map(
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port map(
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aclk=>irq_write, n_areset=>not reset,
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aclk=>irq_write, n_areset=>nReset,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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| Line 90... |
Line 93... |
symbolsPerTransfer=>symbolsPerTransfer,
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symbolsPerTransfer=>symbolsPerTransfer,
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outstandingTransactions=>outstandingTransactions
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outstandingTransactions=>outstandingTransactions
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);
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);
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/* Interrupt-request generator. */
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/* Interrupt-request generator. */
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irq_write<=clk when not reset else '0';
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irq_write<=clk when nReset else '0';
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/* Simulation Tester. */
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/* Simulation Tester. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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clk<=not clk after 10 ps;
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clk<=not clk after 10 ps;
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process is begin
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process is begin
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reset<='0'; wait for 1 ps;
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nReset<='1'; wait for 1 ps;
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reset<='1'; wait for 500 ps;
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nReset<='0'; wait for 500 ps;
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reset<='0';
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nReset<='1';
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Hardware tester. */
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/* Hardware tester. */
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/* Stimuli sequencer. TODO move to tester/stimuli.
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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This emulates the AXI4-Stream Slave.
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*/
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*/
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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process is begin
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process is begin
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/* Fast read. */
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/* Fast read. */
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while not axiMaster_out.tLast loop
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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/* Wait for tValid to assert. */
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| Line 154... |
Line 158... |
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Synthesisable stimuli sequencer. */
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/* Data transmitter. */
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/* Data transmitter. */
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sequencer: process(reset,irq_write) is
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sequencer: process(nReset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in t_addr) is begin
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procedure read(address:in t_addr) is begin
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read(readRequest,address);
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read(readRequest,address);
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end procedure read;
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end procedure read;
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| Line 167... |
Line 174... |
write(request=>writeRequest, address=>(others=>'-'), data=>data);
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write(request=>writeRequest, address=>(others=>'-'), data=>data);
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end procedure write;
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end procedure write;
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variable isPktError:boolean;
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variable isPktError:boolean;
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/* Tester variables. */
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/* Synthesis-only randomisation. */
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/* Simulation-only randomisation. */
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/* Simulation-only randomisation. */
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/* synthesis translate_off */
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variable rv0:RandomPType;
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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begin
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if reset then
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if not nReset then
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/*simulation only. */
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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rv0.InitSeed(rv0'instance_name);
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/* synthesis translate_on */
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txFSM<=idle;
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txFSM<=idle;
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elsif falling_edge(irq_write) then
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elsif falling_edge(irq_write) then
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case txFSM is
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case txFSM is
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when idle=>
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when idle=>
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if outstandingTransactions>0 then
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if outstandingTransactions>0 then
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/* synthesis translate_off */
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write(rv0.RandSigned(axiMaster_out.tData'length));
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write(rv0.RandSigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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txFSM<=transmitting;
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txFSM<=transmitting;
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end if;
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end if;
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when transmitting=>
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when transmitting=>
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if writeResponse.trigger then
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if writeResponse.trigger then
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/* synthesis translate_off */
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write(rv0.RandSigned(axiMaster_out.tData'length));
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write(rv0.RandSigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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end if;
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end if;
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if axiMaster_out.tLast then
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if axiMaster_out.tLast then
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txFSM<=idle;
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txFSM<=idle;
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end if;
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end if;
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| Line 195... |
Line 215... |
end case;
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end case;
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end if;
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end if;
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end process sequencer;
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end process sequencer;
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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process(reset,irq_write) is
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process(nReset,irq_write) is
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/* synthesis translate_off */
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variable rv0:RandomPType;
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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begin
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if reset then
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if not nReset then
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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rv0.InitSeed(rv0'instance_name);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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elsif rising_edge(irq_write) then
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elsif rising_edge(irq_write) then
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if axiMaster_out.tLast then
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if axiMaster_out.tLast then
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/* synthesis translate_off */
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture rtl;
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end architecture rtl;
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No newline at end of file
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No newline at end of file
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