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Line 42... |
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/* synthesis translate_off */
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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/* synthesis translate_on */
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--library altera; use altera.stp;
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entity user is port(
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entity user is port(
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/* Comment-out for simulation. */
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/* Comment-out for simulation. */
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-- clk,nReset:in std_ulogic;
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-- clk,reset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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-- axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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/* Debug ports. */
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/* Debug ports. */
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selTxn:in unsigned(3 downto 0):=x"0"
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);
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);
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end entity user;
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end entity user;
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architecture rtl of user is
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architecture rtl of user is
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signal reset:std_ulogic:='0';
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signal i_reset:std_ulogic:='0';
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signal porCnt:unsigned(3 downto 0);
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signal porCnt:unsigned(3 downto 0);
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signal trigger:boolean;
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/* Global counters. */
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/* Global counters. */
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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signal symbolsPerTransfer:i_transactor.t_cnt;
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signal symbolsPerTransfer:i_transactor.t_cnt;
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signal outstandingTransactions:i_transactor.t_cnt;
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signal outstandingTransactions:i_transactor.t_cnt;
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/* BFM signalling. */
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/* BFM signalling. */
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signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal readResponse,writeResponse:i_transactor.t_bfm;
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signal readResponse,writeResponse:i_transactor.t_bfm;
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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signal clk,nReset:std_ulogic:='0';
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signal clk,reset:std_ulogic:='0';
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attribute period:time; attribute period of clk:signal is 10 ps;
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attribute period:time; attribute period of clk:signal is 10 ps;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(255 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal axiMaster_in:t_axi4StreamTransactor_s2m;
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signal irq_write:std_ulogic; -- clock gating.
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signal irq_write:std_ulogic; -- clock gating.
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signal prbs:i_transactor.t_msg;
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begin
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begin
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/* Bus functional models. */
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/* Bus functional models. */
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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--axiMaster: entity work.axiBfmMaster(simulation)
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port map(
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port map(
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aclk=>irq_write, n_areset=>not reset,
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aclk=>irq_write, n_areset=>not i_reset,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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axiMaster_out=>axiMaster_out,
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symbolsPerTransfer=>symbolsPerTransfer,
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symbolsPerTransfer=>symbolsPerTransfer,
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outstandingTransactions=>outstandingTransactions
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outstandingTransactions=>outstandingTransactions,
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dbg_axiTxFSM=>dbg_axiTxFSM
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);
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);
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/* Interrupt-request generator. */
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/* Clocks and reset. */
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trigger<=txFSM/=i_txFSM or writeResponse.trigger;
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irq_write<=clk when not reset else '0';
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/* Simulation Tester. */
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/* synthesis translate_off */
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clk<=not clk after clk'period/2;
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process is begin
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nReset<='1'; wait for 1 ps;
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nReset<='0'; wait for 500 ps;
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nReset<='1';
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wait;
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end process;
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/* synthesis translate_on */
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/* Hardware tester. */
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/* Power-on Reset circuitry. */
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/* Power-on Reset circuitry. */
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por: process(nReset,clk) is begin
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por: process(reset,clk) is begin
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if not nReset then reset<='1'; porCnt<=(others=>'1');
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if reset then i_reset<='1'; porCnt<=(others=>'1');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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reset<='0';
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i_reset<='0';
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if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;
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if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
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end if;
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end if;
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end process por;
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end process por;
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/*
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process is
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alias trigger is <<signal axiMaster.trigger:boolean>>;
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alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>;
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begin
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-- Remove this assertion once request queue has been implemented.
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if trigger then
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assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error;
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end if;
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wait for clk'period/10;
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end process;
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*/
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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*/
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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clk<=not clk after clk'period/2;
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process is begin
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process is begin
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report "Performing fast read..." severity note;
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reset<='0'; wait for 1 ps;
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reset<='1'; wait for 500 ps;
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/* Fast read. */
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reset<='0';
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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end loop;
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report "Completed fast read..." severity note;
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wait until falling_edge(clk);
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report "Performing normal read..." severity note;
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/* Normal read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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wait until falling_edge(clk);
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end loop;
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report "Completed normal read." severity note;
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wait until falling_edge(clk);
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report "Performing slow read..." severity note;
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/* Slow read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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wait until falling_edge(clk);
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end loop;
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report "Completed slow read." severity note;
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for i in 0 to 10 loop
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wait until falling_edge(clk);
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end loop;
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report "Performing one-shot read..." severity note;
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/* One-shot read. */
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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report "Completed one-shot read." severity note;
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wait;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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/* synthesis translate_on */
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/* Synthesisable stimuli sequencer. */
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/* Simulation Tester. */
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/* Data transmitter. */
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/* Hardware tester. */
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i_prbs: entity tauhop.prbs31(rtl)
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bist: entity work.tester(rtl) port map(
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generic map(
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clk=>clk, reset=>i_reset,
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isParallelLoad=>true,
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axiMaster_in=>axiMaster_in,
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tapVector=>(
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axiMaster_out=>axiMaster_out,
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/* Example polynomial from Wikipedia:
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readRequest=>readRequest, writeRequest=>writeRequest,
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http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
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readResponse=>readResponse, writeResponse=>writeResponse,
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*/
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irq_write=>irq_write,
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0|3|31=>true, 1|2|30 downto 4=>false
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symbolsPerTransfer=>symbolsPerTransfer,
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)
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outstandingTransactions=>outstandingTransactions,
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)
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selTxn=>selTxn
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port map(
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/* Comment-out for simulation. */
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clk=>irq_write, reset=>reset,
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en=>trigger,
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seed=>32x"ace1", --9x"57",
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prbs=>prbs
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);
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);
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sequencer_ns: process(all) is begin
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txFSM<=i_txFSM;
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if reset then txFSM<=idle;
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else
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case i_txFSM is
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when idle=>
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if outstandingTransactions>0 then txFSM<=transmitting; end if;
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when transmitting=>
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if axiMaster_out.tLast then
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txFSM<=idle;
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end if;
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when others=> null;
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end case;
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end if;
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end process sequencer_ns;
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sequencer_op: process(reset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in i_transactor.t_addr) is begin
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i_transactor.read(readRequest,address);
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end procedure read;
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procedure write(data:in i_transactor.t_msg) is begin
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i_transactor.write(request=>writeRequest, address=>(others=>'-'), data=>data);
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end procedure write;
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variable isPktError:boolean;
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/* Tester variables. */
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/* Synthesis-only randomisation. */
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/* Simulation-only randomisation. */
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/* synthesis translate_off */
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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-- if reset then
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/* simulation only. */
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/* synthesis translate_off */
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-- rv0.InitSeed(rv0'instance_name);
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/* synthesis translate_on */
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-- elsif falling_edge(irq_write) then
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if falling_edge(irq_write) then
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case txFSM is
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when transmitting=>
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if trigger then
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/* synthesis translate_off */
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-- write(rv0.RandSigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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write(prbs);
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end if;
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when others=>null;
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end case;
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end if;
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end process sequencer_op;
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sequencer_regs: process(irq_write) is begin
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if falling_edge(irq_write) then
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i_txFSM<=txFSM;
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end if;
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end process sequencer_regs;
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/* Transaction counter. */
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process(reset,symbolsPerTransfer,irq_write) is begin
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if reset then outstandingTransactions<=symbolsPerTransfer;
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elsif rising_edge(irq_write) then
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if not axiMaster_out.tLast then
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if outstandingTransactions<1 then
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outstandingTransactions<=symbolsPerTransfer;
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report "No more pending transactions." severity note;
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elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
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end if;
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end if;
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/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
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if reset then outstandingTransactions<=symbolsPerTransfer; end if;
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end if;
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end process;
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/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
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process(reset,irq_write) is
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/* synthesis translate_off */
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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if reset then
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/* synthesis translate_off */
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rv0.InitSeed(rv0'instance_name);
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
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/* synthesis translate_on */
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elsif rising_edge(irq_write) then
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if axiMaster_out.tLast then
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/* synthesis translate_off */
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symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
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report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
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/* synthesis translate_on */
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end if;
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end if;
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end process;
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end architecture rtl;
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end architecture rtl;
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No newline at end of file
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No newline at end of file
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