| Line 46... |
Line 46... |
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--library altera; use altera.stp;
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--library altera; use altera.stp;
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entity tester is port(
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entity tester is port(
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/* Comment-out for simulation. */
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clk,reset:in std_ulogic;
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clk,reset:in std_ulogic;
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/* AXI Master interface */
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/* AXI Master interface */
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axiMaster_in:buffer t_axi4StreamTransactor_s2m;
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axiMaster_in:buffer t_axi4StreamTransactor_s2m;
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axiMaster_out:in t_axi4StreamTransactor_m2s;
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axiMaster_out:in t_axi4StreamTransactor_m2s;
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/* BFM signalling. */
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/* BFM signalling. */
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-- readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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-- readResponse,writeResponse:t_bfm;
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readRequest,writeRequest:buffer t_bfm;
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readRequest,writeRequest:buffer t_bfm;
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readResponse,writeResponse:in t_bfm;
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readResponse,writeResponse:in t_bfm;
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irq_write:buffer std_ulogic; -- clock gating.
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irq_write:buffer std_ulogic; -- clock gating.
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lastTransaction:out boolean;
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lastTransaction:out boolean;
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/* Debug ports. */
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/* Debug ports. */
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-- dataIn:in t_msg;
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selTxn:in unsigned(3 downto 0)
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selTxn:in unsigned(3 downto 0)
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);
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);
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end entity tester;
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end entity tester;
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architecture rtl of tester is
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architecture rtl of tester is
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-- signal reset:std_ulogic:='0';
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signal locked:std_ulogic;
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signal locked:std_ulogic;
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signal porCnt:unsigned(3 downto 0);
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signal porCnt:unsigned(3 downto 0);
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signal trigger:boolean;
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signal trigger:boolean;
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/* Global counters. */
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/* Global counters. */
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| Line 89... |
Line 84... |
type txStates is (idle,transmitting);
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* Tester signals. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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-- signal clk,nReset:std_ulogic:='0';
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attribute period:time; attribute period of clk:signal is 10 ps;
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attribute period:time; attribute period of clk:signal is 10 ps;
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/* synthesis translate_on */
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/* synthesis translate_on */
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signal testerClk:std_ulogic;
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signal testerClk:std_ulogic;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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| Line 104... |
Line 98... |
-- signal irq_write:std_ulogic; -- clock gating.
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-- signal irq_write:std_ulogic; -- clock gating.
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signal prbs:t_msg;
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signal prbs:t_msg;
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/* Coverage-driven randomisation. */
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/* Coverage-driven randomisation. */
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/* synthesis translate_off */
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shared variable rv0:covPType;
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shared variable rv0:covPType;
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/* synthesis translate_on */
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signal rv:integer;
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signal rv:integer;
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signal pctCovered:real;
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signal pctCovered:real;
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signal isCovered,i_isCovered:boolean;
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signal isCovered,i_isCovered:boolean;
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begin
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begin
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| Line 120... |
Line 116... |
locked=>locked
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locked=>locked
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);
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);
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*/
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*/
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/* Interrupt-request generator. */
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/* Interrupt-request generator. */
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trigger<=txFSM/=i_txFSM or writeResponse.trigger;
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trigger<=txFSM/=i_txFSM or writeResponse.trigger;
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-- trigger<=(txFSM/=i_txFSM and txFSM=transmitting) or writeResponse.trigger; -- fixes bug when multiple transactions occur during endOfTx (this should be illegal).
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irq_write<=clk when not reset else '0';
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irq_write<=clk when not reset else '0';
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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--anlysr_trigger<='1' when writeRequest.trigger else '0';
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anlysr_trigger<='1' when reset else '0';
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anlysr_trigger<='1' when reset else '0';
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| Line 210... |
Line 207... |
axiMaster_in.tReady<=true;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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axiMaster_in.tReady<=false;
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--wait until falling_edge(clk);
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wait until falling_edge(clk);
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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end loop;
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end loop;
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report "coverage: " & to_string(pctCovered) severity note;
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report "coverage: " & to_string(pctCovered) severity note;
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report "Completed normal read." severity note;
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report "Completed normal read." severity note;
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| Line 267... |
Line 264... |
en=>trigger,
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en=>trigger,
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seed=>32x"ace1",
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seed=>32x"ace1",
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prbs=>prbs
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prbs=>prbs
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);
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);
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sequencer_ns: process(all) is begin
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sequencer_ns: process(all) is
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variable last:boolean;
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begin
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txFSM<=i_txFSM;
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txFSM<=i_txFSM;
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if reset then txFSM<=idle;
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if reset then txFSM<=idle;
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else
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else
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case i_txFSM is
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case i_txFSM is
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when idle=>
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when idle=>
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if not lastTransaction then txFSM<=transmitting; end if;
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if not lastTransaction then txFSM<=transmitting; end if;
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last:=false;
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when transmitting=>
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when transmitting=>
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if axiMaster_out.tLast then
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--if axiMaster_out.tLast then
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txFSM<=idle;
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-- txFSM<=idle;
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end if;
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--end if;
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/* Fixes multiple transactions when axiTxState=endOfTx. Do not allow
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txFSM to enter idle until a tReady has been received after the
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last transaction.
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*/
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if lastTransaction then last:=true; end if;
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if axiMaster_in.tReady and last then txFSM<=idle; end if;
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when others=> null;
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when others=> null;
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end case;
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end case;
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end if;
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end if;
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end process sequencer_ns;
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end process sequencer_ns;
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| Line 331... |
Line 339... |
when others=>null;
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when others=>null;
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end case;
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end case;
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end if;
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end if;
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end process sequencer_op;
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end process sequencer_op;
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coverageMonitor: process is
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procedure initialise is begin
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/* simulation only. */
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/* simulation only. */
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/* synthesis translate_off */
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/* synthesis translate_off */
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coverageMonitor: process is
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procedure initialise is begin
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rv0.deallocate; --destroy rv0 and all bins.
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rv0.deallocate; --destroy rv0 and all bins.
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rv0.initSeed(rv0'instance_name);
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rv0.initSeed(rv0'instance_name);
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/* synthesis translate_on */
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end procedure initialise;
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end procedure initialise;
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begin
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begin
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/* Fast- and normal-reads. */
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/* Fast- and normal-reads. */
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for i in 0 to 1 loop
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for i in 0 to 1 loop
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| Line 370... |
Line 378... |
pctCovered<=rv0.getCov;
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pctCovered<=rv0.getCov;
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isCovered<=rv0.isCovered;
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isCovered<=rv0.isCovered;
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i_isCovered<=isCovered;
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i_isCovered<=isCovered;
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end if;
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end if;
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end process;
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end process;
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/* synthesis translate_on */
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sequencer_regs: process(irq_write) is begin
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sequencer_regs: process(irq_write) is begin
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if falling_edge(irq_write) then
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if falling_edge(irq_write) then
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i_txFSM<=txFSM;
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i_txFSM<=txFSM;
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end if;
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end if;
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