| Line 37... |
Line 37... |
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY "user"
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set_global_assignment -name TOP_LEVEL_ENTITY "user"
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#set_global_assignment -name TOP_LEVEL_ENTITY "user"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13 SEPTEMBER 06, 2013"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13 SEPTEMBER 06, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION 12.1
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set_global_assignment -name LAST_QUARTUS_VERSION 12.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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| Line 50... |
Line 49... |
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to reset
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
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# DE2-115
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set_location_assignment PIN_M23 -to nReset
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set_location_assignment PIN_M23 -to nReset
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set_location_assignment PIN_Y2 -to clk
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set_location_assignment PIN_Y2 -to clk
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tauhop-types.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-fsm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/ddr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
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set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
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