| Line 25... |
Line 25... |
//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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OUTFILE PREFIX.v
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INCLUDE def_axi_master.txt
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//////////////////////////////////////
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//////////////////////////////////////
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//
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//
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// General:
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// General:
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// The AXI master has an internal master per ID.
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// The AXI master has an internal master per ID.
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// These internal masters work simultaniously and an interconnect matrix connets them.
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// These internal masters work simultaniously and an interconnect matrix connets them.
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| Line 63... |
Line 58... |
// Description: read a single AXI burst (1 data cycle)
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// Description: read a single AXI burst (1 data cycle)
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// rdata - return read data
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// rdata - return read data
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//
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//
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// check_single(input master_num, input addr, input expected)
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// Description: read a single AXI burst and gives an error if the data read does not match expected
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// Parameters: master_num - number of internal master
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// addr - address
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// expected - expected read data
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//
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// write_and_check_single(input master_num, input addr, input data)
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// Description: write a single AXI burst read it back and compare the write and read data
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// Parameters: master_num - number of internal master
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// addr - address
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// data - data to write and expect on read
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//
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// insert_wr_cmd(input master_num, input addr, input len, input size)
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// insert_wr_cmd(input master_num, input addr, input len, input size)
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// Description: add an AXI write burst to command FIFO
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// Description: add an AXI write burst to command FIFO
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// Parameters: master_num - number of internal master
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// Parameters: master_num - number of internal master
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// addr - address
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// addr - address
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// len - AXI LEN (data strobe number)
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// len - AXI LEN (data strobe number)
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| Line 99... |
Line 106... |
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//
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//
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// Parameters:
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// Parameters:
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//
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//
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// For random testing: (changing these values automatically update interanl masters)
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// For random testing: (changing these values automatically update interanl masters)
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// len_min - minimum burst LEN (length)
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// len_min - minimum burst AXI LEN (length)
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// len_max - maximum burst LEN (length)
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// len_max - maximum burst AXI LEN (length)
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// size_min - minimum burst SIZE (length)
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// size_min - minimum burst AXI SIZE (width)
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// size_max - maximum burst SIZE (length)
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// size_max - maximum burst AXI SIZE (width)
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// addr_min - minimum address (in bytes)
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// addr_min - minimum address (in bytes)
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// addr_max - maximum address (in bytes)
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// addr_max - maximum address (in bytes)
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//
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//
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//////////////////////////////////////
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//////////////////////////////////////
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OUTFILE PREFIX.v
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INCLUDE def_axi_master.txt
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ITER IX ID_NUM
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ITER IX ID_NUM
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module PREFIX(PORTS);
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module PREFIX(PORTS);
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input clk;
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input clk;
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| Line 231... |
Line 242... |
IX : PREFIX_singleIX.read_single(addr, rdata);
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IX : PREFIX_singleIX.read_single(addr, rdata);
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endcase
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endcase
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end
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end
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endtask
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endtask
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task check_single;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] expected;
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begin
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check_master_num("check_single", master_num);
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case (master_num)
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IX : PREFIX_singleIX.check_single(addr, expected);
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endcase
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end
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endtask
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task write_and_check_single;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [DATA_BITS-1:0] data;
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begin
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check_master_num("write_and_check_single", master_num);
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case (master_num)
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IX : PREFIX_singleIX.write_and_check_single(addr, data);
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endcase
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end
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endtask
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task insert_wr_cmd;
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task insert_wr_cmd;
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input [31:0] master_num;
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input [31:0] master_num;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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input [LEN_BITS-1:0] len;
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input [LEN_BITS-1:0] len;
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input [SIZE_BITS-1:0] size;
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input [SIZE_BITS-1:0] size;
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