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[/] [axi_master/] [trunk/] [src/] [base/] [axi_master_single.v] - Diff between revs 6 and 10

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Rev 6 Rev 10
Line 322... Line 322... 
         rd_resp_addr_in = addr;
 
         rd_resp_addr_in = addr;
 
         rd_resp_size_in = size;
 
         rd_resp_size_in = size;
 
 
 
 
 
         if (rd_cmd_full) enable = 1; //start stub not started yet
 
         if (rd_cmd_full) enable = 1; //start stub not started yet
 
 
 
 
 
         wait ((!rd_cmd_full) & (!rd_resp_full));
 
         #FFD; wait ((!rd_cmd_full) & (!rd_resp_full));
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         rd_cmd_push  = 1;
 
         rd_cmd_push  = 1;
 
         rd_resp_push = 1;
 
         rd_resp_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         rd_cmd_push  = 0;
 
         rd_cmd_push  = 0;
Line 347... Line 347... 
         wr_data_len_in  = len;
 
         wr_data_len_in  = len;
 
         wr_data_size_in = size;
 
         wr_data_size_in = size;
 
 
 
 
 
         if (wr_cmd_full) enable = 1; //start stub not started yet
 
         if (wr_cmd_full) enable = 1; //start stub not started yet
 
 
 
 
 
         wait ((!wr_cmd_full) & (!wr_data_full));
 
         #FFD; wait ((!wr_cmd_full) & (!wr_data_full));
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         wr_cmd_push  = 1;
 
         wr_cmd_push  = 1;
 
         wr_data_push = 1;
 
         wr_data_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         wr_cmd_push  = 0;
 
         wr_cmd_push  = 0;
Line 363... Line 363... 
      input [DATA_BITS-1:0]  wdata;
 
      input [DATA_BITS-1:0]  wdata;
 
 
 
 
 
      begin
 
      begin
 
         wr_fifo_data_in  = wdata;
 
         wr_fifo_data_in  = wdata;
 
 
 
 
 
         wait (!wr_fifo_full);
 
         #FFD; wait (!wr_fifo_full);
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         wr_fifo_push = 1;
 
         wr_fifo_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         wr_fifo_push = 0;
 
         wr_fifo_push = 0;
 
      end
 
      end
Line 410... Line 410... 
         scrbrd_enable = 1;
 
         scrbrd_enable = 1;
 
         scrbrd_addr_in  = addr;
 
         scrbrd_addr_in  = addr;
 
         scrbrd_data_in  = data;
 
         scrbrd_data_in  = data;
 
         scrbrd_mask_in  = mask;
 
         scrbrd_mask_in  = mask;
 
 
 
 
 
         wait (!scrbrd_full);
 
         #FFD; wait (!scrbrd_full);
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         scrbrd_push = 1;
 
         scrbrd_push = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         scrbrd_push = 0;
 
         scrbrd_push = 0;
 
      end
 
      end
Line 479... Line 479... 
      reg [ADDR_BITS-1:0]  addr;
 
      reg [ADDR_BITS-1:0]  addr;
 
      reg [LEN_BITS-1:0]   len;
 
      reg [LEN_BITS-1:0]   len;
 
      reg [SIZE_BITS-1:0]  size;
 
      reg [SIZE_BITS-1:0]  size;
 
 
 
 
 
      begin
 
      begin
 
 
 
         if (DATA_BITS==32) size_max = 2'b10;
 
         len   = rand(len_min, len_max);
 
         len   = rand(len_min, len_max);
 
         size  = rand(size_min, size_max);
 
         size  = rand(size_min, size_max);
 
         addr  = rand_align(addr_min, addr_max, 1 << size);
 
         addr  = rand_align(addr_min, addr_max, 1 << size);
 
 
 
 
 
 
 
         if (ahb_bursts)
 
 
 
           begin
 
 
 
              len   =
 
 
 
                      len[3] ? 15 :
 
 
 
                      len[2] ? 7 :
 
 
 
                      len[1] ? 3 : 0;
 
 
 
              if (len > 0)
 
 
 
                size = (DATA_BITS == 64) ? 2'b11 : 2'b10; //AHB bursts always full data
 
 
 
 
 
 
 
              addr = align(addr, EXPR(DATA_BITS/8)*(len+1)); //address aligned to burst size
 
 
 
           end
 
         insert_wr_rd_scrbrd(addr, len, size);
 
         insert_wr_rd_scrbrd(addr, len, size);
 
      end
 
      end
 
   endtask
 
   endtask
 
 
 
 
 
   task insert_rand_chk;
 
   task insert_rand_chk;
Line 525... Line 538... 
      output [1:0] resp;
 
      output [1:0] resp;
 
 
 
 
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [1:0] resp;
 
      reg [1:0] resp;
 
      begin
 
      begin
 
         wait (!rd_fifo_empty);
 
         #FFD; wait (!rd_fifo_empty);
 
         rdata = rd_fifo_data;
 
         rdata = rd_fifo_data;
 
         resp = rd_fifo_resp;
 
         resp = rd_fifo_resp;
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         rd_fifo_pop = 1;
 
         rd_fifo_pop = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
Line 544... Line 557... 
 
 
 
 
      reg [ADDR_BITS-1:0] addr;
 
      reg [ADDR_BITS-1:0] addr;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] rdata;
 
      reg [DATA_BITS-1:0] mask;
 
      reg [DATA_BITS-1:0] mask;
 
      begin
 
      begin
 
         wait (!scrbrd_empty);
 
         #FFD; wait (!scrbrd_empty);
 
         addr = scrbrd_addr;
 
         addr = scrbrd_addr;
 
         rdata = scrbrd_data;
 
         rdata = scrbrd_data;
 
         mask = scrbrd_mask;
 
         mask = scrbrd_mask;
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         scrbrd_pop = 1;
 
         scrbrd_pop = 1;
Line 560... Line 573... 
   task get_wr_resp;
 
   task get_wr_resp;
 
      output [1:0] resp;
 
      output [1:0] resp;
 
 
 
 
 
      reg [1:0] resp;
 
      reg [1:0] resp;
 
      begin
 
      begin
 
         wait (!wr_resp_empty);
 
         #FFD; wait (!wr_resp_empty);
 
         resp = wr_resp_resp;
 
         resp = wr_resp_resp;
 
         @(negedge clk); #FFD;
 
         @(negedge clk); #FFD;
 
         wr_resp_pop = 1;
 
         wr_resp_pop = 1;
 
         @(posedge clk); #FFD;
 
         @(posedge clk); #FFD;
 
         wr_resp_pop = 0;
 
         wr_resp_pop = 0;

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