| Line 49... |
Line 49... |
(MAX_CMDS <= 128) ? 7 :
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(MAX_CMDS <= 128) ? 7 :
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(MAX_CMDS <= 256) ? 8 :
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(MAX_CMDS <= 256) ? 8 :
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(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
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(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal
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input clk;
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input clk;
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input reset;
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input reset;
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port GROUP_STUB_AXI;
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port GROUP_STUB_AXI;
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| Line 73... |
Line 72... |
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reg enable = 0;
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reg enable = 0;
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reg rd_enable = 0;
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reg rd_enable = 0;
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reg wr_enable = 0;
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reg wr_enable = 0;
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reg wait_for_write = 0;
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reg wait_for_write = 0;
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reg err_on_wr_resp = 1;
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reg err_on_rd_resp = 1;
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reg scrbrd_enable = 0;
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reg scrbrd_enable = 0;
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reg [LEN_BITS-1:0] wvalid_cnt;
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reg [LEN_BITS-1:0] wvalid_cnt;
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reg rd_cmd_push = 0;
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reg rd_cmd_push = 0;
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| Line 247... |
Line 248... |
assign ARCACHE = 4'd0; //not supported
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assign ARCACHE = 4'd0; //not supported
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assign ARPROT = 4'd0; //not supported
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assign ARPROT = 4'd0; //not supported
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assign ARLOCK = 2'd0; //not supported
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assign ARLOCK = 2'd0; //not supported
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assign rd_fifo_data_in = RDATA;
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assign rd_fifo_data_in = RDATA;
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assign rd_fifo_resp_in = BRESP;
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assign rd_fifo_resp_in = RRESP;
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assign wr_data_bytes = 1'b1 << wr_data_size;
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assign wr_data_bytes = 1'b1 << wr_data_size;
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assign wr_data_strb =
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assign wr_data_strb =
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wr_data_size == 'd0 ? 1'b1 :
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wr_data_size == 'd0 ? 1'b1 :
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| Line 546... |
Line 547... |
resp = rd_fifo_resp;
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resp = rd_fifo_resp;
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@(negedge clk); #FFD;
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@(negedge clk); #FFD;
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rd_fifo_pop = 1;
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rd_fifo_pop = 1;
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@(posedge clk); #FFD;
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@(posedge clk); #FFD;
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rd_fifo_pop = 0;
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rd_fifo_pop = 0;
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if ((resp != 2'b00) && (err_on_rd_resp))
|
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$display("PREFIX_MASTER%0d: RRESP_ERROR: Received RRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
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end
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end
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endtask
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endtask
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task get_scrbrd;
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task get_scrbrd;
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output [ADDR_BITS-1:0] addr;
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output [ADDR_BITS-1:0] addr;
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| Line 580... |
Line 583... |
resp = wr_resp_resp;
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resp = wr_resp_resp;
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@(negedge clk); #FFD;
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@(negedge clk); #FFD;
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wr_resp_pop = 1;
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wr_resp_pop = 1;
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@(posedge clk); #FFD;
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@(posedge clk); #FFD;
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wr_resp_pop = 0;
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wr_resp_pop = 0;
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if ((resp != 2'b00) && (err_on_wr_resp))
|
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$display("PREFIX_MASTER%0d: BRESP_ERROR: Received BRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time);
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end
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end
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endtask
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endtask
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|
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task insert_rd_single;
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task insert_rd_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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| Line 636... |
Line 641... |
reg [1:0] resp;
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reg [1:0] resp;
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reg [DATA_BITS-1:0] rdata;
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reg [DATA_BITS-1:0] rdata;
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begin
|
begin
|
read_single_ack(addr, rdata, resp);
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read_single_ack(addr, rdata, resp);
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if (rdata !== expected)
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if (rdata !== expected)
|
$display("MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
|
$display("PREFIX_MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time);
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end
|
end
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endtask
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endtask
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|
|
task write_and_check_single;
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task write_and_check_single;
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input [ADDR_BITS-1:0] addr;
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input [ADDR_BITS-1:0] addr;
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| Line 676... |
Line 681... |
get_rd_resp(rdata, resp);
|
get_rd_resp(rdata, resp);
|
expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
|
expected_data = expected_data & mask; //TBD insert z as dontcare (for print)
|
rdata_masked = rdata & mask;
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rdata_masked = rdata & mask;
|
|
|
if (expected_data !== rdata_masked)
|
if (expected_data !== rdata_masked)
|
$display("MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
|
$display("PREFIX_MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time);
|
end
|
end
|
endtask
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endtask
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|
|
always @(posedge scrbrd_enable)
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always @(posedge scrbrd_enable)
|
begin
|
begin
|
