URL https://opencores.org/ocsvn/axi_slave/axi_slave/trunk

Subversion Repositories axi_slave

[/] [axi_slave/] [trunk/] [src/] [base/] [axi_slave_busy.v] - Diff between revs 6 and 10

Rev 6	Rev 10
Line 37...	Line 37...
`include "prgen_rand.v"	`include "prgen_rand.v"

`input clk;`	`input clk;`
`input reset;`	`input reset;`

`input ARREADY_pre;`	`output ARBUSY;`
`input RVALID_pre;`
`input AWREADY_pre;`
`input WREADY_pre;`
`input BVALID_pre;`

`output ARREADY;`
`output RVALID;`
`output AWREADY;`
`output WREADY;`
`output BVALID;`

`output RBUSY;`	`output RBUSY;`
	`output AWBUSY;`
	`output WBUSY;`
`output BBUSY;`	`output BBUSY;`


`reg stall_enable = 1;`	`reg stall_enable = 1;`

Line 87...	Line 78...
`reg AWBUSY;`	`reg AWBUSY;`
`reg WBUSY;`	`reg WBUSY;`
`reg BBUSY;`	`reg BBUSY;`



`assign ARREADY = ARREADY_pre & (~ARBUSY);`
`assign RVALID = RVALID_pre; //in rd_buff`
`assign AWREADY = AWREADY_pre & (~AWBUSY);`
`assign WREADY = WREADY_pre & (~WBUSY);`
`assign BVALID = BVALID_pre; //in wresp`


`task set_stall;`	`task set_stall;`
`reg stall;`	`reg stall;`
`begin`	`begin`
`ar_stall_chance_valid = ar_stall_chance;`	`ar_stall_chance_valid = ar_stall_chance;`
`r_stall_chance_valid = r_stall_chance;`	`r_stall_chance_valid = r_stall_chance;`