| Line 40... |
Line 40... |
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port GROUP_STUB_MEM;
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port GROUP_STUB_MEM;
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//busy
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//busy
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wire ARREADY_pre;
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wire ARBUSY;
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wire RVALID_pre;
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wire AWREADY_pre;
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wire WREADY_pre;
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wire BVALID_pre;
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wire RBUSY;
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wire RBUSY;
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wire AWBUSY;
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wire WBUSY;
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wire BBUSY;
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wire BBUSY;
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//wcmd fifo
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//wcmd fifo
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wire [ADDR_BITS-1:0] wcmd_addr;
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wire [ADDR_BITS-1:0] wcmd_addr;
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wire [ID_BITS-1:0] wcmd_id;
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wire [ID_BITS-1:0] wcmd_id;
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wire [1:0] wcmd_size;
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wire [SIZE_BITS-1:0] wcmd_size;
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wire [LEN_BITS-1:0] wcmd_len;
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wire [LEN_BITS-1:0] wcmd_len;
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wire [1:0] wcmd_resp;
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wire [1:0] wcmd_resp;
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wire wcmd_timeout;
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wire wcmd_timeout;
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wire wcmd_ready;
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wire wcmd_ready;
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wire wcmd_empty;
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wire wcmd_empty;
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wire wcmd_full;
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wire wcmd_full;
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//rcmd fifo
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//rcmd fifo
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wire [ADDR_BITS-1:0] rcmd_addr;
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wire [ADDR_BITS-1:0] rcmd_addr;
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wire [ID_BITS-1:0] rcmd_id;
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wire [ID_BITS-1:0] rcmd_id;
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wire [1:0] rcmd_size;
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wire [SIZE_BITS-1:0] rcmd_size;
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wire [LEN_BITS-1:0] rcmd_len;
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wire [LEN_BITS-1:0] rcmd_len;
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wire [1:0] rcmd_resp;
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wire [1:0] rcmd_resp;
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wire rcmd_timeout;
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wire rcmd_timeout;
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wire rcmd_ready;
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wire rcmd_ready;
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wire rcmd_empty;
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wire rcmd_full;
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wire rcmd_full;
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wire [ID_BITS-1:0] rcmd_id2;
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wire [ID_BITS-1:0] rcmd_id2;
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wire [LEN_BITS-1:0] rcmd_len2;
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wire [LEN_BITS-1:0] rcmd_len2;
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| Line 86... |
Line 85... |
wire RD_last;
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wire RD_last;
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assign RID = rcmd_id2;
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assign RID = rcmd_id2;
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assign ARREADY_pre = (~rcmd_full) & (~AR_stall);
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assign ARREADY = ((~rcmd_full) & (~AR_stall) & (~ARBUSY)) || (~ARVALID);
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assign AWREADY_pre = (~wcmd_full) & (~AW_stall);
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assign AWREADY = ((~wcmd_full) & (~AW_stall) & (~AWBUSY)) || (~AWVALID);
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assign BVALID_pre = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
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assign BVALID = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
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CREATE axi_slave_busy.v
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CREATE axi_slave_busy.v
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PREFIX_busy
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PREFIX_busy
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PREFIX_busy (
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PREFIX_busy (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.ARREADY_pre(ARREADY_pre),
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.ARBUSY(ARBUSY),
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.RVALID_pre(RVALID_pre),
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.AWREADY_pre(AWREADY_pre),
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.WREADY_pre(WREADY_pre),
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.BVALID_pre(BVALID_pre),
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.ARREADY(ARREADY),
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.RVALID(RVALID),
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.AWREADY(AWREADY),
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.WREADY(WREADY),
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.BVALID(BVALID),
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.RBUSY(RBUSY),
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.RBUSY(RBUSY),
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.AWBUSY(AWBUSY),
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.WBUSY(WBUSY),
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.BBUSY(BBUSY)
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.BBUSY(BBUSY)
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);
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);
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CREATE axi_slave_cmd_fifo.v
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CREATE axi_slave_cmd_fifo.v
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PREFIX_cmd_fifo #(WCMD_DEPTH)
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PREFIX_cmd_fifo #(WCMD_DEPTH)
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| Line 179... |
Line 171... |
.cmd_size(),
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.cmd_size(),
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.cmd_len(rcmd_len2),
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.cmd_len(rcmd_len2),
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.cmd_resp(),
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.cmd_resp(),
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.cmd_timeout(),
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.cmd_timeout(),
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.cmd_ready(),
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.cmd_ready(),
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.cmd_empty(),
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.cmd_empty(rcmd_empty),
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.cmd_full(rcmd_full)
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.cmd_full(rcmd_full)
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);
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);
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CREATE axi_slave_wresp_fifo.v
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CREATE axi_slave_wresp_fifo.v
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PREFIX_wresp_fifo #(WCMD_DEPTH)
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PREFIX_wresp_fifo #(WCMD_DEPTH)
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| Line 229... |
Line 221... |
.restart(RD_last),
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.restart(RD_last),
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.ADDR(ADDR_RD)
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.ADDR(ADDR_RD)
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);
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);
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CREATE axi_slave_rd_buff.v
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CREATE axi_slave_rd_buff.v
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PREFIX_rd_buff #(DATA_BITS, ID_BITS)
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PREFIX_rd_buff
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PREFIX_rd_buff(
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PREFIX_rd_buff(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.RD(RD),
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.RD(RD),
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.DOUT(DOUT),
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.DOUT(DOUT),
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.rcmd_len(rcmd_len),
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.rcmd_len(rcmd_len),
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.rcmd_len2(rcmd_len2),
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.rcmd_len2(rcmd_len2),
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.rcmd_resp(rcmd_resp),
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.rcmd_resp(rcmd_resp),
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.rcmd_timeout(rcmd_timeout),
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.rcmd_timeout(rcmd_timeout),
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.rcmd_ready(rcmd_ready),
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.rcmd_ready(rcmd_ready),
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.RVALID(RVALID_pre),
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.RVALID(RVALID),
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.RREADY(RREADY),
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.RREADY(RREADY),
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.RLAST(RLAST),
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.RLAST(RLAST),
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.RDATA(RDATA),
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.RDATA(RDATA),
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.RD_last(RD_last),
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.RD_last(RD_last),
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.RRESP(RRESP),
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.RRESP(RRESP),
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.RBUSY(RBUSY)
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.RBUSY(RBUSY)
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);
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);
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//wr_buff
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//wr_buff
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assign WREADY_pre = (~wcmd_timeout) & (~wcmd_empty);
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assign WREADY = (~wcmd_timeout) & (~wcmd_empty) & (~WBUSY);
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assign WR = WVALID & WREADY & (~wcmd_empty);
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assign WR = WVALID & WREADY & (~wcmd_empty);
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assign DIN = WDATA;
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assign DIN = WDATA;
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assign BSEL = WSTRB;
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assign BSEL = WSTRB;
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