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https://opencores.org/ocsvn/axi_slave/axi_slave/trunk
[/] [axi_slave/] [trunk/] [src/] [base/] [axi_slave_ram.v] - Diff between revs 10 and 11
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Rev 11 |
| Line 84... |
Line 84... |
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wire RD_last;
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wire RD_last;
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assign RID = rcmd_id2;
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assign RID = rcmd_id2;
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//give ready only after VALID comes
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assign ARREADY = ((~rcmd_full) & (~AR_stall) & (~ARBUSY)) & ARVALID;
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assign AWREADY = ((~wcmd_full) & (~AW_stall) & (~AWBUSY)) & AWVALID;
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assign ARREADY = ((~rcmd_full) & (~AR_stall) & (~ARBUSY)) || (~ARVALID);
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// assign ARREADY = ((~rcmd_full) & (~AR_stall) & (~ARBUSY)) || (~ARVALID);
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assign AWREADY = ((~wcmd_full) & (~AW_stall) & (~AWBUSY)) || (~AWVALID);
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// assign AWREADY = ((~wcmd_full) & (~AW_stall) & (~AWBUSY)) || (~AWVALID);
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assign BVALID = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
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assign BVALID = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
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CREATE axi_slave_busy.v
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CREATE axi_slave_busy.v
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PREFIX_busy
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PREFIX_busy
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PREFIX_busy (
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PREFIX_busy (
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Line 245... |
.RRESP(RRESP),
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.RRESP(RRESP),
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.RBUSY(RBUSY)
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.RBUSY(RBUSY)
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);
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);
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//wr_buff
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//wr_buff
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assign WREADY = (~wcmd_timeout) & (~wcmd_empty) & (~WBUSY);
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assign WREADY = (~wcmd_timeout) & (~wcmd_empty) & (~WBUSY) & WVALID;
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assign WR = WVALID & WREADY & (~wcmd_empty);
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assign WR = WVALID & WREADY & (~wcmd_empty);
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assign DIN = WDATA;
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assign DIN = WDATA;
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assign BSEL = WSTRB;
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assign BSEL = WSTRB;
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